forked from OSchip/llvm-project
[VE] Support pack_f32p and pack_f32a intrinsic instructions
Support pack_f32p and pack_f32a intrinsic instructions and regression tests. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D94296
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@ -4,6 +4,13 @@
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let TargetPrefix = "ve" in {
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let TargetPrefix = "ve" in {
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def int_ve_vl_svob : GCCBuiltin<"__builtin_ve_vl_svob">,
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def int_ve_vl_svob : GCCBuiltin<"__builtin_ve_vl_svob">,
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Intrinsic<[], [], [IntrHasSideEffects]>;
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Intrinsic<[], [], [IntrHasSideEffects]>;
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def int_ve_vl_pack_f32p : GCCBuiltin<"__builtin_ve_vl_pack_f32p">,
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Intrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_ptr_ty],
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[IntrReadMem]>;
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def int_ve_vl_pack_f32a : GCCBuiltin<"__builtin_ve_vl_pack_f32a">,
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Intrinsic<[llvm_i64_ty], [llvm_ptr_ty],
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[IntrReadMem]>;
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}
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}
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// Define intrinsics automatically generated
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// Define intrinsics automatically generated
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@ -5,6 +5,18 @@
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// SVOB pattern.
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// SVOB pattern.
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def : Pat<(int_ve_vl_svob), (SVOB)>;
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def : Pat<(int_ve_vl_svob), (SVOB)>;
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// Pack patterns.
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def : Pat<(i64 (int_ve_vl_pack_f32p ADDRrii:$addr0, ADDRrii:$addr1)),
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(ORrr (f2l (LDUrii MEMrii:$addr0)),
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(i2l (LDLZXrii MEMrii:$addr1)))>;
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def : Pat<(i64 (int_ve_vl_pack_f32a ADDRrii:$addr)),
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(MULULrr
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(i2l (LDLZXrii MEMrii:$addr)),
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(LEASLrii (ANDrm (LEAzii 0, 0, (LO32 (i64 0x0000000100000001))),
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!add(32, 64)), 0,
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(HI32 (i64 0x0000000100000001))))>;
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// LSV patterns.
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// LSV patterns.
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def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
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def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
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(LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>;
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(LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>;
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@ -0,0 +1,41 @@
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; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test pack intrinsic instructions
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;;;
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;;; Note:
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;;; We test pack_f32p and pack_f32a pseudo instruction.
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; Function Attrs: nounwind readonly
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define fastcc i64 @pack_f32p(float* readonly %0, float* readonly %1) {
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; CHECK-LABEL: pack_f32p:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ldu %s0, (, %s0)
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; CHECK-NEXT: ldl.zx %s1, (, %s1)
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; CHECK-NEXT: or %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = bitcast float* %0 to i8*
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%4 = bitcast float* %1 to i8*
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%5 = tail call i64 @llvm.ve.vl.pack.f32p(i8* %3, i8* %4)
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ret i64 %5
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}
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; Function Attrs: nounwind readonly
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declare i64 @llvm.ve.vl.pack.f32p(i8*, i8*)
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; Function Attrs: nounwind readonly
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define fastcc i64 @pack_f32a(float* readonly %0) {
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; CHECK-LABEL: pack_f32a:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ldl.zx %s0, (, %s0)
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; CHECK-NEXT: lea %s1, 1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s1, 1(, %s1)
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; CHECK-NEXT: mulu.l %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = bitcast float* %0 to i8*
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%3 = tail call i64 @llvm.ve.vl.pack.f32a(i8* %2)
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ret i64 %3
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}
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; Function Attrs: nounwind readonly
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declare i64 @llvm.ve.vl.pack.f32a(i8*)
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