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[WebAssembly] Implement vector sext_inreg and tests with comparisons 

Summary: Depends on D53251.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D53252

llvm-svn: 344826
This commit is contained in:
Thomas Lively 2018-10-20 01:35:23 +00:00
parent 55735d522d
commit 5ea17d450e
4 changed files with 884 additions and 24 deletions
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4
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
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@ -48,6 +48,8 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
// Booleans always contain 0 or 1.
setBooleanContents(ZeroOrOneBooleanContent);
// Except in SIMD vectors
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
// WebAssembly does not produce floating-point exceptions on normal floating
// point operations.
setHasFloatingPointExceptions(false);
@ -149,6 +151,8 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
for (auto T : {MVT::i8, MVT::i16, MVT::i32})
setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
}
for (auto T : MVT::integer_vector_valuetypes())
setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
// Dynamic stack allocation: use the default expansion.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);

9
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
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@ -613,7 +613,8 @@ multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec,
defm _#vec_t :
SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
[(set (out_t V128:$dst),
(setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond))],
(setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond)
)],
vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>;
}
@ -621,15 +622,15 @@ multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst,
int step = 1> {
defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>;
defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond,
!add(baseInst, step)>;
!add(baseInst, step)>;
defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond,
!add(!add(baseInst, step), step)>;
!add(!add(baseInst, step), step)>;
}
multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
!add(baseInst, 1)>;
!add(baseInst, 1)>;
}
// Equality: eq

830
llvm/test/CodeGen/WebAssembly/simd-comparisons.ll
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File diff suppressed because it is too large Load Diff

65
llvm/test/CodeGen/WebAssembly/simd-sext-inreg.ll Normal file
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@ -0,0 +1,65 @@
; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
; Test that vector sign extensions lower to shifts
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown"
; CHECK-LABEL: sext_inreg_v16i8:
; NO-SIMD128-NOT: i8x16
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 7{{$}}
; SIMD128-NEXT: i8x16.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 7{{$}}
; SIMD128-NEXT: i8x16.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <16 x i8> @sext_inreg_v16i8(<16 x i1> %x) {
%res = sext <16 x i1> %x to <16 x i8>
ret <16 x i8> %res
}
; CHECK-LABEL: sext_inreg_v8i16:
; NO-SIMD128-NOT: i16x8
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 15{{$}}
; SIMD128-NEXT: i16x8.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 15{{$}}
; SIMD128-NEXT: i16x8.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <8 x i16> @sext_inreg_v8i16(<8 x i1> %x) {
%res = sext <8 x i1> %x to <8 x i16>
ret <8 x i16> %res
}
; CHECK-LABEL: sext_inreg_v4i32:
; NO-SIMD128-NOT: i32x4
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 31{{$}}
; SIMD128-NEXT: i32x4.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 31{{$}}
; SIMD128-NEXT: i32x4.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @sext_inreg_v4i32(<4 x i1> %x) {
%res = sext <4 x i1> %x to <4 x i32>
ret <4 x i32> %res
}
; CHECK-LABEL: sext_inreg_v2i64:
; NO-SIMD128-NOT: i64x2
; SDIM128-VM-NOT: i64x2
; SIMD128-NEXT: .param v128{{$}}
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 63{{$}}
; SIMD128-NEXT: i64x2.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 63{{$}}
; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @sext_inreg_v2i64(<2 x i1> %x) {
%res = sext <2 x i1> %x to <2 x i64>
ret <2 x i64> %res
}