Add support for the x86-64 'q' regigster modifier, and add support for the

b/h/w/k/q inline asm memory modifiers, which are just ignored.  This fixes
PR1748 and CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll

llvm-svn: 43430
This commit is contained in:
Chris Lattner 2007-10-29 03:09:07 +00:00
parent ceced4ca73
commit 5e99fd8c0d
2 changed files with 29 additions and 2 deletions

View File

@ -521,6 +521,9 @@ bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
case 'k': // Print SImode register
Reg = getX86SubSuperRegister(Reg, MVT::i32);
break;
case 'q': // Print DImode register
Reg = getX86SubSuperRegister(Reg, MVT::i64);
break;
}
O << '%';
@ -547,6 +550,7 @@ bool X86ATTAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
case 'h': // Print QImode high register
case 'w': // Print HImode register
case 'k': // Print SImode register
case 'q': // Print DImode register
if (MI->getOperand(OpNo).isRegister())
return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]);
printOperand(MI, OpNo);
@ -566,8 +570,20 @@ bool X86ATTAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
unsigned OpNo,
unsigned AsmVariant,
const char *ExtraCode) {
if (ExtraCode && ExtraCode[0])
return true; // Unknown modifier.
if (ExtraCode && ExtraCode[0]) {
if (ExtraCode[1] != 0) return true; // Unknown modifier.
switch (ExtraCode[0]) {
default: return true; // Unknown modifier.
case 'b': // Print QImode register
case 'h': // Print QImode high register
case 'w': // Print HImode register
case 'k': // Print SImode register
case 'q': // Print SImode register
// These only apply to registers, ignore on mem.
break;
}
}
printMemReference(MI, OpNo);
return false;
}

View File

@ -0,0 +1,11 @@
; RUN: llvm-as < %s | llc
; PR1748
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
define i32 @kernel_init(i8* %unused) {
entry:
call void asm sideeffect "foo ${0:q}", "=*imr"( i64* null )
ret i32 0
}