[mips] Some uses of isMips64()/hasMips64() are really tests for 64-bit GPR's

Summary:
No functional change since these predicates are (currently) synonymous.

Extracted from a patch by David Chisnall
His work was sponsored by: DARPA, AFRL

Differential Revision: http://llvm-reviews.chandlerc.com/D3202

llvm-svn: 204943

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

@@ -215,8 +215,8 @@ class MipsAsmParser : public MCTargetAsmParser {
 
   MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
 
-  bool isMips64() const {
+  bool isGP64() const {
-    return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
+    return (STI.getFeatureBits() & Mips::FeatureGP64Bit) != 0;
   }
 
   bool isFP64() const {
@@ -879,7 +879,7 @@ void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
   const MCExpr *ExprOffset;
   unsigned TmpRegNum;
   unsigned AtRegNum = getReg(
-      (isMips64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
+      (isGP64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
   // 1st operand is either the source or destination register.
   assert(Inst.getOperand(0).isReg() && "expected register operand kind");
   unsigned RegOpNum = Inst.getOperand(0).getReg();
@@ -1210,11 +1210,10 @@ unsigned MipsAsmParser::getReg(int RC, int RegNo) {
 }
 
 unsigned MipsAsmParser::getGPR(int RegNo) {
-  return getReg((isMips64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
+  return getReg(isGP64() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
-                 RegNo);
+                RegNo);
 }
 
-
 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
   if (RegNum >
       getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
@@ -1279,7 +1278,7 @@ MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
     SMLoc S = Parser.getTok().getLoc();
     Parser.Lex(); // Eat dollar token.
     // Parse the register operand.
-    if (!tryParseRegisterOperand(Operands, isMips64())) {
+    if (!tryParseRegisterOperand(Operands, isGP64())) {
       if (getLexer().is(AsmToken::LParen)) {
         // Check if it is indexed addressing operand.
         Operands.push_back(MipsOperand::CreateToken("(", S));
@@ -1288,7 +1287,7 @@ MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
           return true;
 
         Parser.Lex(); // Eat the dollar
-        if (tryParseRegisterOperand(Operands, isMips64()))
+        if (tryParseRegisterOperand(Operands, isGP64()))
           return true;
 
         if (!getLexer().is(AsmToken::RParen))
@@ -1495,7 +1494,7 @@ bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
                                   SMLoc &EndLoc) {
   StartLoc = Parser.getTok().getLoc();
-  RegNo = tryParseRegister(isMips64());
+  RegNo = tryParseRegister(isGP64());
   EndLoc = Parser.getTok().getLoc();
   return (RegNo == (unsigned)-1);
 }
@@ -1562,7 +1561,7 @@ MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
 
         // Zero register assumed, add a memory operand with ZERO as its base.
         Operands.push_back(MipsOperand::CreateMem(
-            isMips64() ? Mips::ZERO_64 : Mips::ZERO, IdVal, S, E));
+            isGP64() ? Mips::ZERO_64 : Mips::ZERO, IdVal, S, E));
         return MatchOperand_Success;
       }
       Error(Parser.getTok().getLoc(), "'(' expected");
@@ -1572,8 +1571,8 @@ MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
     Parser.Lex(); // Eat the '(' token.
   }
 
-  Res = parseRegs(Operands, isMips64() ? (int)MipsOperand::Kind_GPR64
+  Res = parseRegs(Operands, isGP64() ? (int)MipsOperand::Kind_GPR64
-                                       : (int)MipsOperand::Kind_GPR32);
+                                     : (int)MipsOperand::Kind_GPR32);
   if (Res != MatchOperand_Success)
     return Res;
 
@@ -1965,7 +1964,7 @@ MipsAsmParser::parseMSACtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
 MipsAsmParser::OperandMatchResultTy
 MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
 
-  if (!isMips64())
+  if (!isGP64())
     return MatchOperand_NoMatch;
   return parseRegs(Operands, (int)MipsOperand::Kind_GPR64);
 }
@@ -2147,8 +2146,8 @@ bool MipsAsmParser::searchSymbolAlias(
         APInt IntVal(32, -1);
         if (!DefSymbol.substr(1).getAsInteger(10, IntVal))
           RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
-                                         isMips64() ? Mips::GPR64RegClassID
+                                         isGP64() ? Mips::GPR64RegClassID
-                                                    : Mips::GPR32RegClassID);
+                                                  : Mips::GPR32RegClassID);
         else {
           // Lookup for the register with the corresponding name.
           switch (Kind) {

llvm/lib/Target/Mips/MipsISelLowering.cpp

@@ -3029,9 +3029,9 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
           return std::make_pair(0U, &Mips::CPU16RegsRegClass);
         return std::make_pair(0U, &Mips::GPR32RegClass);
       }
-      if (VT == MVT::i64 && !hasMips64())
+      if (VT == MVT::i64 && !isGP64bit())
         return std::make_pair(0U, &Mips::GPR32RegClass);
-      if (VT == MVT::i64 && hasMips64())
+      if (VT == MVT::i64 && isGP64bit())
         return std::make_pair(0U, &Mips::GPR64RegClass);
       // This will generate an error message
       return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));

llvm/lib/Target/Mips/MipsISelLowering.h

@@ -433,6 +433,7 @@ namespace llvm {
     const MipsSubtarget *Subtarget;
 
     bool hasMips64() const { return Subtarget->hasMips64(); }
+    bool isGP64bit() const { return Subtarget->isGP64bit(); }
     bool isO32() const { return Subtarget->isABI_O32(); }
     bool isN32() const { return Subtarget->isABI_N32(); }
     bool isN64() const { return Subtarget->isABI_N64(); }

llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

@@ -657,7 +657,7 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
   case ISD::ConstantFP: {
     ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
     if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
-      if (Subtarget.hasMips64()) {
+      if (Subtarget.isGP64bit()) {
         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
                                               Mips::ZERO_64, MVT::i64);
         Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);

llvm/lib/Target/Mips/MipsSEISelLowering.cpp

@@ -38,7 +38,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
   // Set up the register classes
   addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
 
-  if (hasMips64())
+  if (isGP64bit())
     addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
 
   if (Subtarget->hasDSP() || Subtarget->hasMSA()) {

llvm/lib/Target/Mips/MipsSubtarget.cpp

@@ -117,8 +117,8 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
           ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
 
   // Check if Architecture and ABI are compatible.
-  assert(((!hasMips64() && (isABI_O32() || isABI_EABI())) ||
+  assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
-          (hasMips64() && (isABI_N32() || isABI_N64()))) &&
+          (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
          "Invalid  Arch & ABI pair.");
 
   if (hasMSA() && !isFP64bit())
@@ -143,8 +143,8 @@ MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
                                      RegClassVector &CriticalPathRCs) const {
   Mode = TargetSubtargetInfo::ANTIDEP_NONE;
   CriticalPathRCs.clear();
-  CriticalPathRCs.push_back(hasMips64() ?
+  CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
-                            &Mips::GPR64RegClass : &Mips::GPR32RegClass);
+                                        : &Mips::GPR32RegClass);
   return OptLevel >= CodeGenOpt::Aggressive;
 }