forked from OSchip/llvm-project
[NFC][MC] Use [MC]Register in MachineVerifier
Differential Revision: https://reviews.llvm.org/D89815
This commit is contained in:
Mircea Trofin
parent
c17ae2916c
commit
5e731625f3
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@ -102,10 +102,10 @@ namespace {
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bool isFunctionRegBankSelected;
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bool isFunctionSelected;
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using RegVector = SmallVector<unsigned, 16>;
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using RegVector = SmallVector<Register, 16>;
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using RegMaskVector = SmallVector<const uint32_t *, 4>;
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using RegSet = DenseSet<unsigned>;
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using RegMap = DenseMap<unsigned, const MachineInstr *>;
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using RegSet = DenseSet<Register>;
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using RegMap = DenseMap<Register, const MachineInstr *>;
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using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
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const MachineInstr *FirstNonPHI;
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@ -120,10 +120,10 @@ namespace {
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SlotIndex lastIndex;
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// Add Reg and any sub-registers to RV
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void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
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void addRegWithSubRegs(RegVector &RV, Register Reg) {
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RV.push_back(Reg);
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if (Register::isPhysicalRegister(Reg))
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for (const MCPhysReg &SubReg : TRI->subregs(Reg))
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if (Reg.isPhysical())
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for (const MCPhysReg &SubReg : TRI->subregs(Reg.asMCReg()))
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RV.push_back(SubReg);
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}
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@ -159,8 +159,8 @@ namespace {
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// Add register to vregsRequired if it belongs there. Return true if
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// anything changed.
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bool addRequired(unsigned Reg) {
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if (!Register::isVirtualRegister(Reg))
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bool addRequired(Register Reg) {
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if (!Reg.isVirtual())
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return false;
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if (regsLiveOut.count(Reg))
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return false;
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@ -170,7 +170,7 @@ namespace {
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// Same for a full set.
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bool addRequired(const RegSet &RS) {
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bool Changed = false;
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for (unsigned Reg : RS)
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for (Register Reg : RS)
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Changed |= addRequired(Reg);
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return Changed;
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}
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@ -184,7 +184,7 @@ namespace {
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}
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// Live-out registers are either in regsLiveOut or vregsPassed.
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bool isLiveOut(unsigned Reg) const {
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bool isLiveOut(Register Reg) const {
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return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
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}
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};
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@ -192,13 +192,13 @@ namespace {
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// Extra register info per MBB.
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DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
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bool isReserved(unsigned Reg) {
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return Reg < regsReserved.size() && regsReserved.test(Reg);
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bool isReserved(Register Reg) {
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return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
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}
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bool isAllocatable(unsigned Reg) const {
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return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
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!regsReserved.test(Reg);
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bool isAllocatable(Register Reg) const {
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return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
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!regsReserved.test(Reg.id());
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}
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// Analysis information if available
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@ -226,7 +226,7 @@ namespace {
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LLT MOVRegType = LLT{});
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void report_context(const LiveInterval &LI) const;
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void report_context(const LiveRange &LR, unsigned VRegUnit,
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void report_context(const LiveRange &LR, Register VRegUnit,
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LaneBitmask LaneMask) const;
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void report_context(const LiveRange::Segment &S) const;
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void report_context(const VNInfo &VNI) const;
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@ -234,18 +234,19 @@ namespace {
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void report_context(MCPhysReg PhysReg) const;
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void report_context_liverange(const LiveRange &LR) const;
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void report_context_lanemask(LaneBitmask LaneMask) const;
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void report_context_vreg(unsigned VReg) const;
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void report_context_vreg_regunit(unsigned VRegOrUnit) const;
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void report_context_vreg(Register VReg) const;
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void report_context_vreg_regunit(Register VRegOrUnit) const;
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void verifyInlineAsm(const MachineInstr *MI);
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void checkLiveness(const MachineOperand *MO, unsigned MONum);
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void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
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SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
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SlotIndex UseIdx, const LiveRange &LR,
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Register VRegOrUnit,
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LaneBitmask LaneMask = LaneBitmask::getNone());
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void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
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SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
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bool SubRangeCheck = false,
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SlotIndex DefIdx, const LiveRange &LR,
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Register VRegOrUnit, bool SubRangeCheck = false,
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LaneBitmask LaneMask = LaneBitmask::getNone());
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void markReachable(const MachineBasicBlock *MBB);
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@ -256,12 +257,12 @@ namespace {
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void verifyLiveVariables();
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void verifyLiveIntervals();
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void verifyLiveInterval(const LiveInterval&);
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void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
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void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
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LaneBitmask);
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void verifyLiveRangeSegment(const LiveRange&,
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const LiveRange::const_iterator I, unsigned,
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void verifyLiveRangeSegment(const LiveRange &,
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const LiveRange::const_iterator I, Register,
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LaneBitmask);
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void verifyLiveRange(const LiveRange&, unsigned,
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void verifyLiveRange(const LiveRange &, Register,
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LaneBitmask LaneMask = LaneBitmask::getNone());
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void verifyStackFrame();
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@ -508,7 +509,7 @@ void MachineVerifier::report_context(const LiveInterval &LI) const {
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errs() << "- interval: " << LI << '\n';
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}
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void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
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void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
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LaneBitmask LaneMask) const {
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report_context_liverange(LR);
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report_context_vreg_regunit(VRegUnit);
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@ -532,11 +533,11 @@ void MachineVerifier::report_context(MCPhysReg PReg) const {
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errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
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}
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void MachineVerifier::report_context_vreg(unsigned VReg) const {
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void MachineVerifier::report_context_vreg(Register VReg) const {
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errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
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}
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void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
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void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
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if (Register::isVirtualRegister(VRegOrUnit)) {
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report_context_vreg(VRegOrUnit);
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} else {
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@ -1958,8 +1959,10 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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}
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void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
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unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
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LaneBitmask LaneMask) {
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unsigned MONum, SlotIndex UseIdx,
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const LiveRange &LR,
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Register VRegOrUnit,
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LaneBitmask LaneMask) {
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LiveQueryResult LRQ = LR.Query(UseIdx);
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// Check if we have a segment at the use, note however that we only need one
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// live subregister range, the others may be dead.
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@ -1980,8 +1983,11 @@ void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
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}
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void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
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unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
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bool SubRangeCheck, LaneBitmask LaneMask) {
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unsigned MONum, SlotIndex DefIdx,
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const LiveRange &LR,
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Register VRegOrUnit,
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bool SubRangeCheck,
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LaneBitmask LaneMask) {
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if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
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assert(VNI && "NULL valno is not allowed");
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if (VNI->def != DefIdx) {
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@ -2025,7 +2031,7 @@ void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
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void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
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const MachineInstr *MI = MO->getParent();
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const unsigned Reg = MO->getReg();
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const Register Reg = MO->getReg();
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// Both use and def operands can read a register.
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if (MO->readsReg()) {
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@ -2043,8 +2049,9 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
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if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
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SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
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// Check the cached regunit intervals.
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if (Register::isPhysicalRegister(Reg) && !isReserved(Reg)) {
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for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
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if (Reg.isPhysical() && !isReserved(Reg)) {
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for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
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++Units) {
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if (MRI->isReservedRegUnit(*Units))
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continue;
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if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
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@ -2190,9 +2197,9 @@ void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
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// Kill any masked registers.
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while (!regMasks.empty()) {
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const uint32_t *Mask = regMasks.pop_back_val();
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for (unsigned Reg : regsLive)
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if (Register::isPhysicalRegister(Reg) &&
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MachineOperand::clobbersPhysReg(Mask, Reg))
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for (Register Reg : regsLive)
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if (Reg.isPhysical() &&
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MachineOperand::clobbersPhysReg(Mask, Reg.asMCReg()))
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regsDead.push_back(Reg);
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}
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set_subtract(regsLive, regsDead); regsDead.clear();
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@ -2225,7 +2232,7 @@ struct VRegFilter {
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// Add elements to the filter itself. \pre Input set \p FromRegSet must have
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// no duplicates. Both virtual and physical registers are fine.
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template <typename RegSetT> void add(const RegSetT &FromRegSet) {
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SmallVector<unsigned, 0> VRegsBuffer;
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SmallVector<Register, 0> VRegsBuffer;
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filterAndAdd(FromRegSet, VRegsBuffer);
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}
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// Filter \p FromRegSet through the filter and append passed elements into \p
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@ -2233,13 +2240,13 @@ struct VRegFilter {
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// \returns true if anything changed.
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template <typename RegSetT>
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bool filterAndAdd(const RegSetT &FromRegSet,
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SmallVectorImpl<unsigned> &ToVRegs) {
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SmallVectorImpl<Register> &ToVRegs) {
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unsigned SparseUniverse = Sparse.size();
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unsigned NewSparseUniverse = SparseUniverse;
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unsigned NewDenseSize = Dense.size();
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size_t Begin = ToVRegs.size();
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for (unsigned Reg : FromRegSet) {
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if (!Register::isVirtualRegister(Reg))
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for (Register Reg : FromRegSet) {
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if (!Reg.isVirtual())
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continue;
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unsigned Index = Register::virtReg2Index(Reg);
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if (Index < SparseUniverseMax) {
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@ -2263,7 +2270,7 @@ struct VRegFilter {
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Sparse.resize(NewSparseUniverse);
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Dense.reserve(NewDenseSize);
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for (unsigned I = Begin; I < End; ++I) {
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unsigned Reg = ToVRegs[I];
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Register Reg = ToVRegs[I];
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unsigned Index = Register::virtReg2Index(Reg);
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if (Index < SparseUniverseMax)
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Sparse.set(Index);
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@ -2296,7 +2303,7 @@ private:
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// universe). filter_b implicitly contains all physical registers at all times.
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class FilteringVRegSet {
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VRegFilter Filter;
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SmallVector<unsigned, 0> VRegs;
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SmallVector<Register, 0> VRegs;
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public:
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// Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
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@ -2474,7 +2481,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
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// Check for killed virtual registers that should be live out.
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for (const auto &MBB : *MF) {
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BBInfo &MInfo = MBBInfoMap[&MBB];
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for (unsigned VReg : MInfo.vregsRequired)
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for (Register VReg : MInfo.vregsRequired)
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if (MInfo.regsKilled.count(VReg)) {
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report("Virtual register killed in block, but needed live out.", &MBB);
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errs() << "Virtual register " << printReg(VReg)
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@ -2484,7 +2491,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
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if (!MF->empty()) {
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BBInfo &MInfo = MBBInfoMap[&MF->front()];
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for (unsigned VReg : MInfo.vregsRequired) {
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for (Register VReg : MInfo.vregsRequired) {
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report("Virtual register defs don't dominate all uses.", MF);
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report_context_vreg(VReg);
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}
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@ -2543,8 +2550,8 @@ void MachineVerifier::visitMachineFunctionAfter() {
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void MachineVerifier::verifyLiveVariables() {
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assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = Register::index2VirtReg(i);
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for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
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Register Reg = Register::index2VirtReg(I);
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LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
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for (const auto &MBB : *MF) {
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BBInfo &MInfo = MBBInfoMap[&MBB];
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@ -2569,8 +2576,8 @@ void MachineVerifier::verifyLiveVariables() {
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void MachineVerifier::verifyLiveIntervals() {
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assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = Register::index2VirtReg(i);
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for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
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Register Reg = Register::index2VirtReg(I);
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// Spilling and splitting may leave unused registers around. Skip them.
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if (MRI->reg_nodbg_empty(Reg))
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@ -2594,7 +2601,7 @@ void MachineVerifier::verifyLiveIntervals() {
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}
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void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
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const VNInfo *VNI, unsigned Reg,
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const VNInfo *VNI, Register Reg,
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LaneBitmask LaneMask) {
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if (VNI->isUnused())
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return;
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@ -2687,8 +2694,8 @@ void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
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void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
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const LiveRange::const_iterator I,
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unsigned Reg, LaneBitmask LaneMask)
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{
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Register Reg,
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LaneBitmask LaneMask) {
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const LiveRange::Segment &S = *I;
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const VNInfo *VNI = S.valno;
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assert(VNI && "Live segment has no valno");
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@ -2899,7 +2906,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
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}
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}
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void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
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void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
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LaneBitmask LaneMask) {
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for (const VNInfo *VNI : LR.valnos)
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verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
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@ -2909,7 +2916,7 @@ void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
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}
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void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
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unsigned Reg = LI.reg();
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Register Reg = LI.reg();
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assert(Register::isVirtualRegister(Reg));
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verifyLiveRange(LI, Reg);
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