diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp index ed5ef30af260..2b1ebee4e21b 100644 --- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -180,7 +180,7 @@ void AggressiveAntiDepBreaker::FinishBlock() { State = nullptr; } -void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, +void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count, unsigned InsertPosIndex) { assert(Count < InsertPosIndex && "Instruction index out of expected range!"); @@ -190,7 +190,7 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, ScanInstruction(MI, Count); DEBUG(dbgs() << "Observe: "); - DEBUG(MI->dump()); + DEBUG(MI.dump()); DEBUG(dbgs() << "\tRegs:"); std::vector &DefIndices = State->GetDefIndices(); @@ -214,9 +214,8 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, DEBUG(dbgs() << '\n'); } -bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI, - MachineOperand& MO) -{ +bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI, + MachineOperand &MO) { if (!MO.isReg() || !MO.isImplicit()) return false; @@ -226,19 +225,19 @@ bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI, MachineOperand *Op = nullptr; if (MO.isDef()) - Op = MI->findRegisterUseOperand(Reg, true); + Op = MI.findRegisterUseOperand(Reg, true); else - Op = MI->findRegisterDefOperand(Reg); + Op = MI.findRegisterDefOperand(Reg); return(Op && Op->isImplicit()); } -void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI, - std::set& PassthruRegs) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); +void AggressiveAntiDepBreaker::GetPassthruRegs( + MachineInstr &MI, std::set &PassthruRegs) { + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI.getOperand(i); if (!MO.isReg()) continue; - if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) || + if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) || IsImplicitDefUse(MI, MO)) { const unsigned Reg = MO.getReg(); for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); @@ -332,9 +331,8 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, DEBUG(if (!header && footer) dbgs() << footer); } -void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, - unsigned Count, - std::set& PassthruRegs) { +void AggressiveAntiDepBreaker::PrescanInstruction( + MachineInstr &MI, unsigned Count, std::set &PassthruRegs) { std::vector &DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); @@ -344,8 +342,8 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, // dead, or because only a subregister is live at the def. If we // don't do this the dead def will be incorrectly merged into the // previous def. - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; @@ -354,8 +352,8 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, } DEBUG(dbgs() << "\tDef Groups:"); - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; @@ -367,8 +365,8 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, // defined in a call must not be changed (ABI). Inline assembly may // reference either system calls or the register directly. Skip it until we // can tell user specified registers from compiler-specified. - if (MI->isCall() || MI->hasExtraDefRegAllocReq() || - TII->isPredicated(*MI) || MI->isInlineAsm()) { + if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || + MI.isInlineAsm()) { DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); State->UnionGroups(Reg, 0); } @@ -386,8 +384,8 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, // Note register reference... const TargetRegisterClass *RC = nullptr; - if (i < MI->getDesc().getNumOperands()) - RC = TII->getRegClass(MI->getDesc(), i, TRI, MF); + if (i < MI.getDesc().getNumOperands()) + RC = TII->getRegClass(MI.getDesc(), i, TRI, MF); AggressiveAntiDepState::RegisterReference RR = { &MO, RC }; RegRefs.insert(std::make_pair(Reg, RR)); } @@ -396,13 +394,13 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, // Scan the register defs for this instruction and update // live-ranges. - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; // Ignore KILLs and passthru registers for liveness... - if (MI->isKill() || (PassthruRegs.count(Reg) != 0)) + if (MI.isKill() || (PassthruRegs.count(Reg) != 0)) continue; // Update def for Reg and aliases. @@ -421,7 +419,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, } } -void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI, +void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) { DEBUG(dbgs() << "\tUse Groups:"); std::multimap& @@ -444,13 +442,13 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI, // instruction which may not be executed. The second R6 def may or may not // re-define R6 so it's not safe to change it since the last R6 use cannot be // changed. - bool Special = MI->isCall() || MI->hasExtraSrcRegAllocReq() || - TII->isPredicated(*MI) || MI->isInlineAsm(); + bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() || + TII->isPredicated(MI) || MI.isInlineAsm(); // Scan the register uses for this instruction and update // live-ranges, groups and RegRefs. - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; @@ -470,8 +468,8 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI, // Note register reference... const TargetRegisterClass *RC = nullptr; - if (i < MI->getDesc().getNumOperands()) - RC = TII->getRegClass(MI->getDesc(), i, TRI, MF); + if (i < MI.getDesc().getNumOperands()) + RC = TII->getRegClass(MI.getDesc(), i, TRI, MF); AggressiveAntiDepState::RegisterReference RR = { &MO, RC }; RegRefs.insert(std::make_pair(Reg, RR)); } @@ -480,12 +478,12 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI, // Form a group of all defs and uses of a KILL instruction to ensure // that all registers are renamed as a group. - if (MI->isKill()) { + if (MI.isKill()) { DEBUG(dbgs() << "\tKill Group:"); unsigned FirstReg = 0; - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI.getOperand(i); if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; @@ -793,13 +791,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( unsigned Count = InsertPosIndex - 1; for (MachineBasicBlock::iterator I = End, E = Begin; I != E; --Count) { - MachineInstr *MI = --I; + MachineInstr &MI = *--I; - if (MI->isDebugValue()) + if (MI.isDebugValue()) continue; DEBUG(dbgs() << "Anti: "); - DEBUG(MI->dump()); + DEBUG(MI.dump()); std::set PassthruRegs; GetPassthruRegs(MI, PassthruRegs); @@ -810,13 +808,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( // The dependence edges that represent anti- and output- // dependencies that are candidates for breaking. std::vector Edges; - const SUnit *PathSU = MISUnitMap[MI]; + const SUnit *PathSU = MISUnitMap[&MI]; AntiDepEdges(PathSU, Edges); // If MI is not on the critical path, then we don't rename // registers in the CriticalPathSet. BitVector *ExcludeRegs = nullptr; - if (MI == CriticalPathMI) { + if (&MI == CriticalPathMI) { CriticalPathSU = CriticalPathStep(CriticalPathSU); CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr; } else if (CriticalPathSet.any()) { @@ -825,7 +823,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( // Ignore KILL instructions (they form a group in ScanInstruction // but don't cause any anti-dependence breaking themselves) - if (!MI->isKill()) { + if (!MI.isKill()) { // Attempt to break each anti-dependency... for (unsigned i = 0, e = Edges.size(); i != e; ++i) { const SDep *Edge = Edges[i]; @@ -855,7 +853,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( continue; } else { // No anti-dep breaking for implicit deps - MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg); + MachineOperand *AntiDepOp = MI.findRegisterDefOperand(AntiDepReg); assert(AntiDepOp && "Can't find index for defined register operand"); if (!AntiDepOp || AntiDepOp->isImplicit()) { DEBUG(dbgs() << " (implicit)\n"); @@ -939,7 +937,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( for (DbgValueVector::iterator DVI = DbgValues.begin(), DVE = DbgValues.end(); DVI != DVE; ++DVI) if (DVI->second == Q.second.Operand->getParent()) - UpdateDbgValue(DVI->first, AntiDepReg, NewReg); + UpdateDbgValue(*DVI->first, AntiDepReg, NewReg); } // We just went back in time and modified history; the diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h index eba738396606..f97e6666b219 100644 --- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h +++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.h @@ -144,7 +144,7 @@ class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState { /// Update liveness information to account for the current /// instruction, which will not be scheduled. /// - void Observe(MachineInstr *MI, unsigned Count, + void Observe(MachineInstr &MI, unsigned Count, unsigned InsertPosIndex) override; /// Finish anti-dep breaking for a basic block. @@ -156,19 +156,19 @@ class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState { /// Return true if MO represents a register /// that is both implicitly used and defined in MI - bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO); + bool IsImplicitDefUse(MachineInstr &MI, MachineOperand &MO); /// If MI implicitly def/uses a register, then /// return that register and all subregisters. - void GetPassthruRegs(MachineInstr *MI, std::set& PassthruRegs); + void GetPassthruRegs(MachineInstr &MI, std::set &PassthruRegs); void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag, const char *header = nullptr, const char *footer = nullptr); - void PrescanInstruction(MachineInstr *MI, unsigned Count, - std::set& PassthruRegs); - void ScanInstruction(MachineInstr *MI, unsigned Count); + void PrescanInstruction(MachineInstr &MI, unsigned Count, + std::set &PassthruRegs); + void ScanInstruction(MachineInstr &MI, unsigned Count); BitVector GetRenameRegisters(unsigned Reg); bool FindSuitableFreeRegisters(unsigned AntiDepGroupIndex, RenameOrderType& RenameOrder, diff --git a/llvm/lib/CodeGen/AntiDepBreaker.h b/llvm/lib/CodeGen/AntiDepBreaker.h index 2aa77161bcf2..04f7f419f5ea 100644 --- a/llvm/lib/CodeGen/AntiDepBreaker.h +++ b/llvm/lib/CodeGen/AntiDepBreaker.h @@ -47,19 +47,18 @@ public: /// Update liveness information to account for the current /// instruction, which will not be scheduled. - virtual void Observe(MachineInstr *MI, unsigned Count, - unsigned InsertPosIndex) =0; - + virtual void Observe(MachineInstr &MI, unsigned Count, + unsigned InsertPosIndex) = 0; + /// Finish anti-dep breaking for a basic block. virtual void FinishBlock() =0; /// Update DBG_VALUE if dependency breaker is updating /// other machine instruction to use NewReg. - void UpdateDbgValue(MachineInstr *MI, unsigned OldReg, unsigned NewReg) { - assert(MI && "Expected valid instruction"); - assert (MI->isDebugValue() && "MI is not DBG_VALUE!"); - if (MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg) - MI->getOperand(0).setReg(NewReg); + void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg) { + assert(MI.isDebugValue() && "MI is not DBG_VALUE!"); + if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg) + MI.getOperand(0).setReg(NewReg); } }; diff --git a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp index 06673ae3f307..d693af4a0a2d 100644 --- a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -87,7 +87,7 @@ void CriticalAntiDepBreaker::FinishBlock() { KeepRegs.reset(); } -void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, +void CriticalAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count, unsigned InsertPosIndex) { // Kill instructions can define registers but are really nops, and there might // be a real definition earlier that needs to be paired with uses dominated by @@ -96,7 +96,7 @@ void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, // FIXME: It may be possible to remove the isKill() restriction once PR18663 // has been properly fixed. There can be value in processing kills as seen in // the AggressiveAntiDepBreaker class. - if (MI->isDebugValue() || MI->isKill()) + if (MI.isDebugValue() || MI.isKill()) return; assert(Count < InsertPosIndex && "Instruction index out of expected range!"); @@ -146,7 +146,7 @@ static const SDep *CriticalPathStep(const SUnit *SU) { return Next; } -void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) { +void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) { // It's not safe to change register allocation for source operands of // instructions that have special allocation requirements. Also assume all // registers used in a call must not be changed (ABI). @@ -164,19 +164,19 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) { // re-define R6 so it's not safe to change it since the last R6 use cannot be // changed. bool Special = - MI->isCall() || MI->hasExtraSrcRegAllocReq() || TII->isPredicated(*MI); + MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI); // Scan the register operands for this instruction and update // Classes and RegRefs. - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI.getOperand(i); if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; const TargetRegisterClass *NewRC = nullptr; - if (i < MI->getDesc().getNumOperands()) - NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF); + if (i < MI.getDesc().getNumOperands()) + NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); // For now, only allow the register to be changed if its register // class is consistent across all uses. @@ -211,7 +211,7 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) { // of a register? In the above 'xor' example, the uses of %eax are undef, so // earlier instructions could still replace %eax even though the 'xor' // itself can't be changed. - if (MI->isRegTiedToUseOperand(i) && + if (MI.isRegTiedToUseOperand(i) && Classes[Reg] == reinterpret_cast(-1)) { for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); SubRegs.isValid(); ++SubRegs) { @@ -233,18 +233,17 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) { } } -void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI, - unsigned Count) { +void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) { // Update liveness. // Proceeding upwards, registers that are defed but not used in this // instruction are now dead. - assert(!MI->isKill() && "Attempting to scan a kill instruction"); + assert(!MI.isKill() && "Attempting to scan a kill instruction"); - if (!TII->isPredicated(*MI)) { + if (!TII->isPredicated(MI)) { // Predicated defs are modeled as read + write, i.e. similar to two // address updates. - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI.getOperand(i); if (MO.isRegMask()) for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) @@ -265,7 +264,8 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI, if (KeepRegs.test(Reg)) continue; // Ignore two-addr defs. - if (MI->isRegTiedToUseOperand(i)) continue; + if (MI.isRegTiedToUseOperand(i)) + continue; // For the reg itself and all subregs: update the def to current; // reset the kill state, any restrictions, and references. @@ -282,16 +282,16 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI, Classes[*SR] = reinterpret_cast(-1); } } - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI.getOperand(i); if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; if (!MO.isUse()) continue; const TargetRegisterClass *NewRC = nullptr; - if (i < MI->getDesc().getNumOperands()) - NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF); + if (i < MI.getDesc().getNumOperands()) + NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); // For now, only allow the register to be changed if its register // class is consistent across all uses. @@ -509,7 +509,7 @@ BreakAntiDependencies(const std::vector& SUnits, unsigned Broken = 0; unsigned Count = InsertPosIndex - 1; for (MachineBasicBlock::iterator I = End, E = Begin; I != E; --Count) { - MachineInstr *MI = --I; + MachineInstr &MI = *--I; // Kill instructions can define registers but are really nops, and there // might be a real definition earlier that needs to be paired with uses // dominated by this kill. @@ -517,7 +517,7 @@ BreakAntiDependencies(const std::vector& SUnits, // FIXME: It may be possible to remove the isKill() restriction once PR18663 // has been properly fixed. There can be value in processing kills as seen // in the AggressiveAntiDepBreaker class. - if (MI->isDebugValue() || MI->isKill()) + if (MI.isDebugValue() || MI.isKill()) continue; // Check if this instruction has a dependence on the critical path that @@ -534,7 +534,7 @@ BreakAntiDependencies(const std::vector& SUnits, // edge per instruction. Note that we'd have to be able to break all of // the anti-dependencies in an instruction in order to be effective. unsigned AntiDepReg = 0; - if (MI == CriticalPathMI) { + if (&MI == CriticalPathMI) { if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) { const SUnit *NextSU = Edge->getSUnit(); @@ -584,7 +584,7 @@ BreakAntiDependencies(const std::vector& SUnits, // If MI's defs have a special allocation requirement, don't allow // any def registers to be changed. Also assume all registers // defined in a call must not be changed (ABI). - if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(*MI)) + if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) // If this instruction's defs have special allocation requirement, don't // break this anti-dependency. AntiDepReg = 0; @@ -593,8 +593,8 @@ BreakAntiDependencies(const std::vector& SUnits, // is invalid. If the instruction defines other registers, // save a list of them so that we don't pick a new register // that overlaps any of them. - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI.getOperand(i); if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; @@ -646,7 +646,7 @@ BreakAntiDependencies(const std::vector& SUnits, for (DbgValueVector::iterator DVI = DbgValues.begin(), DVE = DbgValues.end(); DVI != DVE; ++DVI) if (DVI->second == Q->second->getParent()) - UpdateDbgValue(DVI->first, AntiDepReg, NewReg); + UpdateDbgValue(*DVI->first, AntiDepReg, NewReg); } // We just went back in time and modified history; the diff --git a/llvm/lib/CodeGen/CriticalAntiDepBreaker.h b/llvm/lib/CodeGen/CriticalAntiDepBreaker.h index 10b873959ad0..ac0dac638437 100644 --- a/llvm/lib/CodeGen/CriticalAntiDepBreaker.h +++ b/llvm/lib/CodeGen/CriticalAntiDepBreaker.h @@ -84,15 +84,15 @@ class LLVM_LIBRARY_VISIBILITY CriticalAntiDepBreaker : public AntiDepBreaker { /// Update liveness information to account for the current /// instruction, which will not be scheduled. - void Observe(MachineInstr *MI, unsigned Count, + void Observe(MachineInstr &MI, unsigned Count, unsigned InsertPosIndex) override; /// Finish anti-dep breaking for a basic block. void FinishBlock() override; private: - void PrescanInstruction(MachineInstr *MI); - void ScanInstruction(MachineInstr *MI, unsigned Count); + void PrescanInstruction(MachineInstr &MI); + void ScanInstruction(MachineInstr &MI, unsigned Count); bool isNewRegClobberedByRefs(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned NewReg); diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index b95dffd05c46..06a88bfb4c61 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -169,7 +169,7 @@ namespace { /// Observe - Update liveness information to account for the current /// instruction, which will not be scheduled. /// - void Observe(MachineInstr *MI, unsigned Count); + void Observe(MachineInstr &MI, unsigned Count); /// finishBlock - Clean up register live-range state. /// @@ -335,7 +335,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { Scheduler.EmitSchedule(); Current = MI; CurrentCount = Count; - Scheduler.Observe(MI, CurrentCount); + Scheduler.Observe(*MI, CurrentCount); } I = MI; if (MI->isBundle()) @@ -414,7 +414,7 @@ void SchedulePostRATDList::schedule() { /// Observe - Update liveness information to account for the current /// instruction, which will not be scheduled. /// -void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) { +void SchedulePostRATDList::Observe(MachineInstr &MI, unsigned Count) { if (AntiDepBreak) AntiDepBreak->Observe(MI, Count, EndIndex); }