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[X86][F16C] Fix btver2 AGU pipe scheduling 

Use the store AGU for stores, and the load AGU needs to be the first pipe for loads

llvm-svn: 316771
This commit is contained in:
Simon Pilgrim 2017-10-27 16:34:58 +00:00
parent decd8a702a
commit 5e3808afa2
1 changed files with 3 additions and 3 deletions
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6
llvm/lib/Target/X86/X86ScheduleBtVer2.td
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@ -428,13 +428,13 @@ def WriteCVT3: SchedWriteRes<[JFPU1]> {
def : InstRW<[WriteCVT3], (instregex "VCVTPS2PHrr")>;
def : InstRW<[WriteCVT3], (instregex "VCVTPH2PSrr")>;
def WriteCVT3St: SchedWriteRes<[JFPU1, JLAGU]> {
def WriteCVT3St: SchedWriteRes<[JFPU1, JSAGU]> {
let Latency = 3;
let ResourceCycles = [1, 1];
}
def : InstRW<[WriteCVT3St], (instregex "VCVTPS2PHmr")>;
def WriteCVT3Ld: SchedWriteRes<[JFPU1, JLAGU]> {
def WriteCVT3Ld: SchedWriteRes<[JLAGU, JFPU1]> {
let Latency = 8;
let ResourceCycles = [1, 1];
}
@ -447,7 +447,7 @@ def WriteCVTPS2PHY: SchedWriteRes<[JFPU1, JFPU01]> {
}
def : InstRW<[WriteCVTPS2PHY], (instregex "VCVTPS2PHYrr")>;
def WriteCVTPS2PHYSt: SchedWriteRes<[JFPU1, JFPU01, JLAGU]> {
def WriteCVTPS2PHYSt: SchedWriteRes<[JFPU1, JFPU01, JSAGU]> {
let Latency = 11;
let ResourceCycles = [2,2,1];
let NumMicroOps = 3;