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[mips] Correct operand order in DSP's mthi/mtlo 

Summary: The result register is the second operand as per the other mt* instructions.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D15993

llvm-svn: 257478
This commit is contained in:
Daniel Sanders 2016-01-12 15:15:14 +00:00
parent b5b5a1d7ad
commit 5e1d5a789a
2 changed files with 10 additions and 9 deletions
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5
llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
View File

@ -544,8 +544,6 @@ void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
// Add lo/hi registers if the mtlo/hi instructions created have explicit
// def registers.
@ -556,6 +554,9 @@ void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
LoInst.addReg(DstLo, RegState::Define);
HiInst.addReg(DstHi, RegState::Define);
}
LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
}
void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,

14
llvm/test/CodeGen/Mips/madd-msub.ll
View File

@ -18,7 +18,7 @@
; 32-DAG: [[m]]flo $3
; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]]
; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}}
; DSP-DAG: mfhi $2, $[[AC]]
; DSP-DAG: mflo $3, $[[AC]]
@ -64,7 +64,7 @@ entry:
; 32-DAG: [[m]]flo $3
; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]]
; DSP-DAG: maddu $[[AC]], ${{[45]}}, ${{[45]}}
; DSP-DAG: mfhi $2, $[[AC]]
; DSP-DAG: mflo $3, $[[AC]]
@ -101,8 +101,8 @@ entry:
; 32-DAG: [[m]]fhi $2
; 32-DAG: [[m]]flo $3
; DSP-DAG: mthi $[[AC:ac[0-3]+]], $6
; DSP-DAG: mtlo $[[AC]], $7
; DSP-DAG: mthi $6, $[[AC:ac[0-3]+]]
; DSP-DAG: mtlo $7, $[[AC]]
; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}}
; DSP-DAG: mfhi $2, $[[AC]]
; DSP-DAG: mflo $3, $[[AC]]
@ -143,7 +143,7 @@ entry:
; 32-DAG: [[m]]flo $3
; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]]
; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}}
; DSP-DAG: mfhi $2, $[[AC]]
; DSP-DAG: mflo $3, $[[AC]]
@ -189,7 +189,7 @@ entry:
; 32-DAG: [[m]]flo $3
; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]]
; DSP-DAG: msubu $[[AC]], ${{[45]}}, ${{[45]}}
; DSP-DAG: mfhi $2, $[[AC]]
; DSP-DAG: mflo $3, $[[AC]]
@ -229,7 +229,7 @@ entry:
; 32-DAG: [[m]]flo $3
; DSP-DAG: addiu $[[T0:[0-9]+]], $zero, 0
; DSP-DAG: mtlo $[[AC:ac[0-3]+]], $6
; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]]
; DSP-DAG: msub $[[AC]], ${{[45]}}, ${{[45]}}
; DSP-DAG: mfhi $2, $[[AC]]
; DSP-DAG: mflo $3, $[[AC]]