forked from OSchip/llvm-project
parent
8bbd3650a6
commit
5e0d6b509a
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@ -26452,9 +26452,9 @@ static SDValue combineBasicSADPattern(SDNode *Extract, SelectionDAG &DAG,
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// in the SAD vector.
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unsigned Stages = Log2_32(VT.getVectorNumElements());
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MVT SadVT = SAD.getSimpleValueType();
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if (Stages > 3) {
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if (Stages > 3) {
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unsigned SadElems = SadVT.getVectorNumElements();
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for(unsigned i = Stages - 3; i > 0; --i) {
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SmallVector<int, 16> Mask(SadElems, -1);
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for(unsigned j = 0, MaskEnd = 1 << (i - 1); j < MaskEnd; ++j)
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@ -26465,11 +26465,10 @@ static SDValue combineBasicSADPattern(SDNode *Extract, SelectionDAG &DAG,
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SAD = DAG.getNode(ISD::ADD, DL, SadVT, SAD, Shuffle);
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}
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}
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// Return the lowest i32.
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MVT ResVT = MVT::getVectorVT(MVT::i32, SadVT.getSizeInBits() / 32);
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SAD = DAG.getNode(ISD::BITCAST, DL, ResVT, SAD);
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MVT ResVT = MVT::getVectorVT(MVT::i32, SadVT.getSizeInBits() / 32);
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SAD = DAG.getNode(ISD::BITCAST, DL, ResVT, SAD);
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, SAD,
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Extract->getOperand(1));
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}
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@ -30868,7 +30867,7 @@ static SDValue combineLoopSADPattern(SDNode *N, SelectionDAG &DAG,
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// We only handle v16i32 for SSE2 / v32i32 for AVX2 / v64i32 for AVX512.
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// TODO: We should be able to handle larger vectors by splitting them before
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// feeding them into several SADs, and then reducing over those.
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// feeding them into several SADs, and then reducing over those.
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if (VT.getSizeInBits() / 4 > RegSize)
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return SDValue();
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