forked from OSchip/llvm-project
[DivRemPairs] Add srem-of-srem tests (PR42823, D65298, D65451)
The @srem_of_srem_expanded case exposed a RAUW pitfall in D65298. Right now these don't appear to fail verification, so it should be safe to precommit them. https://reviews.llvm.org/D65298 https://bugs.llvm.org/show_bug.cgi?id=42823 https://reviews.llvm.org/D65451 llvm-svn: 367325
This commit is contained in:
Roman Lebedev
parent
39f3503814
commit
5e0adce40f
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@ -95,6 +95,51 @@ end:
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ret i8 %ret
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}
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; Be careful with RAUW/invalidation if this is a srem-of-srem.
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define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_unexpanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[T1]], [[T0]]
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; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[X]], [[TMP1]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[TMP2]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: ret i32 [[TMP4]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3.recomposed = srem i32 %X, %t0
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%t4 = sdiv i32 %t3.recomposed, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6.recomposed = srem i32 %t3.recomposed, %Y
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ret i32 %t6.recomposed
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}
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define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_expanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
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; CHECK-NEXT: ret i32 [[T6]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3 = sub nsw i32 %X, %t2
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%t4 = sdiv i32 %t3, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6 = sub nsw i32 %t3, %t5
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ret i32 %t6
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}
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; If the target doesn't have a unified div/rem op for the type, keep decomposed rem
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define i128 @dont_hoist_urem(i128 %a, i128 %b) {
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@ -151,6 +151,51 @@ end:
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ret i8 %ret
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}
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; Be careful with RAUW/invalidation if this is a srem-of-srem.
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define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_unexpanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[T1]], [[T0]]
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; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[X]], [[TMP1]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[TMP2]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: ret i32 [[TMP4]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3.recomposed = srem i32 %X, %t0
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%t4 = sdiv i32 %t3.recomposed, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6.recomposed = srem i32 %t3.recomposed, %Y
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ret i32 %t6.recomposed
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}
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define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_expanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
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; CHECK-NEXT: ret i32 [[T6]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3 = sub nsw i32 %X, %t2
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%t4 = sdiv i32 %t3, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6 = sub nsw i32 %t3, %t5
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ret i32 %t6
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}
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; If the ops don't match, don't do anything: signedness.
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define i32 @dont_hoist_udiv(i32 %a, i32 %b) {
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@ -95,6 +95,49 @@ end:
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ret i8 %ret
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}
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; Be careful with RAUW/invalidation if this is a srem-of-srem.
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define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_unexpanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3_RECOMPOSED:%.*]] = srem i32 [[X]], [[T0]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6_RECOMPOSED:%.*]] = srem i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: ret i32 [[T6_RECOMPOSED]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3.recomposed = srem i32 %X, %t0
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%t4 = sdiv i32 %t3.recomposed, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6.recomposed = srem i32 %t3.recomposed, %Y
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ret i32 %t6.recomposed
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}
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define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_expanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
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; CHECK-NEXT: ret i32 [[T6]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3 = sub nsw i32 %X, %t2
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%t4 = sdiv i32 %t3, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6 = sub nsw i32 %t3, %t5
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ret i32 %t6
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}
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; If the target doesn't have a unified div/rem op for the type, keep decomposed rem
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define i128 @dont_hoist_urem(i128 %a, i128 %b) {
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@ -145,6 +145,49 @@ end:
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ret i8 %ret
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}
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; Be careful with RAUW/invalidation if this is a srem-of-srem.
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define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_unexpanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3_RECOMPOSED:%.*]] = srem i32 [[X]], [[T0]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6_RECOMPOSED:%.*]] = srem i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: ret i32 [[T6_RECOMPOSED]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3.recomposed = srem i32 %X, %t0
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%t4 = sdiv i32 %t3.recomposed, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6.recomposed = srem i32 %t3.recomposed, %Y
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ret i32 %t6.recomposed
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}
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define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_expanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
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; CHECK-NEXT: ret i32 [[T6]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3 = sub nsw i32 %X, %t2
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%t4 = sdiv i32 %t3, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6 = sub nsw i32 %t3, %t5
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ret i32 %t6
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}
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; If the ops don't match, don't do anything: signedness.
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define i32 @dont_hoist_udiv(i32 %a, i32 %b) {
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