forked from OSchip/llvm-project
AMDGPU: Support non-entry block static sized allocas
OpenMP emits these for some reason, so handle them. Assume these use 4096 bytes by default, with a flag to override this. Also change the related stack assumption for calls to have a flag.
This commit is contained in:
Matt Arsenault
parent
dda82986f9
commit
5e007fe998
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@ -49,6 +49,22 @@ using namespace llvm;
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using namespace llvm::AMDGPU;
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using namespace llvm::AMDGPU::HSAMD;
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// We need to tell the runtime some amount ahead of time if we don't know the
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// true stack size. Assume a smaller number if this is only due to dynamic /
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// non-entry block allocas.
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static cl::opt<uint32_t> AssumedStackSizeForExternalCall(
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"amdgpu-assume-external-call-stack-size",
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cl::desc("Assumed stack use of any external call (in bytes)"),
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cl::Hidden,
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cl::init(16384));
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static cl::opt<uint32_t> AssumedStackSizeForDynamicSizeObjects(
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"amdgpu-assume-dynamic-stack-object-size",
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cl::desc("Assumed extra stack use if there are any "
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"variable sized objects (in bytes)"),
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cl::Hidden,
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cl::init(4096));
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// This should get the default rounding mode from the kernel. We just set the
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// default here, but this could change if the OpenCL rounding mode pragmas are
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// used.
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@ -637,8 +653,13 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
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Info.UsesFlatScratch = false;
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}
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Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
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Info.PrivateSegmentSize = FrameInfo.getStackSize();
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// Assume a big number if there are any unknown sized objects.
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Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
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if (Info.HasDynamicallySizedStack)
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Info.PrivateSegmentSize += AssumedStackSizeForDynamicSizeObjects;
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if (MFI->isStackRealigned())
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Info.PrivateSegmentSize += FrameInfo.getMaxAlign().value();
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@ -907,7 +928,9 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
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MaxVGPR = std::max(MaxVGPR, 23);
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MaxAGPR = std::max(MaxAGPR, 23);
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CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
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CalleeFrameSize = std::max(CalleeFrameSize,
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static_cast<uint64_t>(AssumedStackSizeForExternalCall));
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Info.UsesVCC = true;
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Info.UsesFlatScratch = ST.hasFlatAddressSpace();
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Info.HasDynamicallySizedStack = true;
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@ -3089,6 +3089,67 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
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IsThisReturn ? OutVals[0] : SDValue());
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}
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// This is identical to the default implementation in ExpandDYNAMIC_STACKALLOC,
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// except for applying the wave size scale to the increment amount.
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SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(
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SDValue Op, SelectionDAG &DAG) const {
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const MachineFunction &MF = DAG.getMachineFunction();
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const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
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SDLoc dl(Op);
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EVT VT = Op.getValueType();
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SDValue Tmp1 = Op;
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SDValue Tmp2 = Op.getValue(1);
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SDValue Tmp3 = Op.getOperand(2);
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SDValue Chain = Tmp1.getOperand(0);
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Register SPReg = Info->getStackPtrOffsetReg();
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// Chain the dynamic stack allocation so that it doesn't modify the stack
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// pointer when other instructions are using the stack.
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Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
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SDValue Size = Tmp2.getOperand(1);
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SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
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Chain = SP.getValue(1);
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unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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const TargetFrameLowering *TFL = ST.getFrameLowering();
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unsigned Opc =
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TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp ?
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ISD::ADD : ISD::SUB;
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SDValue ScaledSize = DAG.getNode(
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ISD::SHL, dl, VT, Size,
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DAG.getConstant(ST.getWavefrontSizeLog2(), dl, MVT::i32));
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unsigned StackAlign = TFL->getStackAlignment();
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Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value
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if (Align > StackAlign)
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Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
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DAG.getConstant(-(uint64_t)Align, dl, VT));
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Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
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Tmp2 = DAG.getCALLSEQ_END(
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Chain, DAG.getIntPtrConstant(0, dl, true),
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DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
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return DAG.getMergeValues({Tmp1, Tmp2}, dl);
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}
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SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
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SelectionDAG &DAG) const {
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// We only handle constant sizes here to allow non-entry block, static sized
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// allocas. A truly dynamic value is more difficult to support because we
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// don't know if the size value is uniform or not. If the size isn't uniform,
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// we would need to do a wave reduction to get the maximum size to know how
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// much to increment the uniform stack pointer.
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SDValue Size = Op.getOperand(1);
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if (isa<ConstantSDNode>(Size))
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return lowerDYNAMIC_STACKALLOCImpl(Op, DAG); // Use "generic" expansion.
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return AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(Op, DAG);
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}
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Register SITargetLowering::getRegisterByName(const char* RegName, LLT VT,
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const MachineFunction &MF) const {
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Register Reg = StringSwitch<Register>(RegName)
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@ -4305,6 +4366,8 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::FMINNUM_IEEE:
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case ISD::FMAXNUM_IEEE:
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return splitBinaryVectorOp(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC:
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return LowerDYNAMIC_STACKALLOC(Op, DAG);
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}
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return SDValue();
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}
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@ -337,6 +337,9 @@ public:
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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Register getRegisterByName(const char* RegName, LLT VT,
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const MachineFunction &MF) const override;
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@ -0,0 +1,271 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,DEFAULTSIZE %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -amdgpu-assume-dynamic-stack-object-size=1024 < %s | FileCheck -check-prefixes=GCN,ASSUME1024 %s
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; FIXME: Generated test checks do not check metadata at the end of the
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; function, so this also includes manually added checks.
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; Test that we can select a statically sized alloca outside of the
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; entry block.
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; FIXME: FunctionLoweringInfo unhelpfully doesn't preserve an
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; alignment less than the stack alignment.
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define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align4(i32 addrspace(1)* %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) {
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; GCN-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align4:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s9
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; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
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; GCN-NEXT: s_add_u32 s0, s0, s9
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; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
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; GCN-NEXT: s_addc_u32 s1, s1, 0
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; GCN-NEXT: s_mov_b32 s33, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_lg_u32 s8, 0
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; GCN-NEXT: s_cbranch_scc1 BB0_3
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; GCN-NEXT: ; %bb.1: ; %bb.0
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; GCN-NEXT: s_cmp_lg_u32 s9, 0
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; GCN-NEXT: s_cbranch_scc1 BB0_3
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; GCN-NEXT: ; %bb.2: ; %bb.1
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; GCN-NEXT: s_add_i32 s6, s32, 0x1000
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; GCN-NEXT: s_lshl_b32 s7, s10, 2
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; GCN-NEXT: s_mov_b32 s32, s6
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; GCN-NEXT: v_mov_b32_e32 v2, s6
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_add_i32 s6, s6, s7
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; GCN-NEXT: v_mov_b32_e32 v3, 1
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; GCN-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
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; GCN-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4
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; GCN-NEXT: v_mov_b32_e32 v1, s6
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; GCN-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_add_u32_e32 v2, v1, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: global_store_dword v[0:1], v2, off
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; GCN-NEXT: BB0_3: ; %bb.2
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: global_store_dword v[0:1], v0, off
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; GCN-NEXT: s_endpgm
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entry:
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%cond0 = icmp eq i32 %arg.cond0, 0
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br i1 %cond0, label %bb.0, label %bb.2
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bb.0:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
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%gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
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%cond1 = icmp eq i32 %arg.cond1, 0
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br i1 %cond1, label %bb.1, label %bb.2
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bb.1:
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; Use the alloca outside of the defining block.
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store i32 0, i32 addrspace(5)* %gep0
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store i32 1, i32 addrspace(5)* %gep1
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%gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
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%load = load i32, i32 addrspace(5)* %gep2
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%add = add i32 %load, %tid
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store i32 %add, i32 addrspace(1)* %out
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br label %bb.2
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bb.2:
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store volatile i32 0, i32 addrspace(1)* undef
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ret void
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}
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; DEFAULTSIZE: .amdhsa_private_segment_fixed_size 4112
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; DEFAULTSIZE: ; ScratchSize: 4112
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; ASSUME1024: .amdhsa_private_segment_fixed_size 1040
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; ASSUME1024: ; ScratchSize: 1040
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define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align64(i32 addrspace(1)* %out, i32 %arg.cond, i32 %in) {
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; GCN-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s9
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; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
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; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8
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; GCN-NEXT: s_add_u32 s0, s0, s9
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; GCN-NEXT: s_addc_u32 s1, s1, 0
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; GCN-NEXT: s_mov_b32 s33, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_lg_u32 s6, 0
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; GCN-NEXT: s_cbranch_scc1 BB1_2
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; GCN-NEXT: ; %bb.1: ; %bb.0
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; GCN-NEXT: s_add_i32 s6, s32, 0x1000
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; GCN-NEXT: s_andn2_b32 s6, s6, 63
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; GCN-NEXT: s_lshl_b32 s7, s7, 2
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; GCN-NEXT: s_mov_b32 s32, s6
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; GCN-NEXT: v_mov_b32_e32 v2, s6
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_add_i32 s6, s6, s7
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; GCN-NEXT: v_mov_b32_e32 v3, 1
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; GCN-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
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; GCN-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4
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; GCN-NEXT: v_mov_b32_e32 v1, s6
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; GCN-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_add_u32_e32 v2, v1, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: global_store_dword v[0:1], v2, off
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; GCN-NEXT: BB1_2: ; %bb.1
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: global_store_dword v[0:1], v0, off
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; GCN-NEXT: s_endpgm
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entry:
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%cond = icmp eq i32 %arg.cond, 0
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br i1 %cond, label %bb.0, label %bb.1
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bb.0:
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%alloca = alloca [16 x i32], align 64, addrspace(5)
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%gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
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%gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
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store i32 0, i32 addrspace(5)* %gep0
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store i32 1, i32 addrspace(5)* %gep1
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%gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
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%load = load i32, i32 addrspace(5)* %gep2
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%add = add i32 %load, %tid
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store i32 %add, i32 addrspace(1)* %out
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br label %bb.1
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bb.1:
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store volatile i32 0, i32 addrspace(1)* undef
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ret void
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}
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; DEFAULTSIZE: .amdhsa_private_segment_fixed_size 4160
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; DEFAULTSIZE: ; ScratchSize: 4160
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; ASSUME1024: .amdhsa_private_segment_fixed_size 1088
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; ASSUME1024: ; ScratchSize: 1088
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define void @func_non_entry_block_static_alloca_align4(i32 addrspace(1)* %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) {
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; GCN-LABEL: func_non_entry_block_static_alloca_align4:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s7, s33
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
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; GCN-NEXT: s_mov_b32 s33, s32
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; GCN-NEXT: s_add_u32 s32, s32, 0x400
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; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; GCN-NEXT: s_cbranch_execz BB2_3
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; GCN-NEXT: ; %bb.1: ; %bb.0
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
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; GCN-NEXT: s_and_b64 exec, exec, vcc
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; GCN-NEXT: s_cbranch_execz BB2_3
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; GCN-NEXT: ; %bb.2: ; %bb.1
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; GCN-NEXT: s_add_i32 s6, s32, 0x1000
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: v_mov_b32_e32 v3, s6
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; GCN-NEXT: v_mov_b32_e32 v6, 1
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; GCN-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
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; GCN-NEXT: buffer_store_dword v6, v3, s[0:3], 0 offen offset:4
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; GCN-NEXT: v_lshl_add_u32 v2, v4, 2, s6
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; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
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; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v5
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; GCN-NEXT: s_mov_b32 s32, s6
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_add_u32_e32 v2, v2, v3
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; GCN-NEXT: global_store_dword v[0:1], v2, off
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; GCN-NEXT: BB2_3: ; %bb.2
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; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: global_store_dword v[0:1], v0, off
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; GCN-NEXT: s_sub_u32 s32, s32, 0x400
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; GCN-NEXT: s_mov_b32 s33, s7
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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entry:
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%cond0 = icmp eq i32 %arg.cond0, 0
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br i1 %cond0, label %bb.0, label %bb.2
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bb.0:
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
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%gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
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%cond1 = icmp eq i32 %arg.cond1, 0
|
||||
br i1 %cond1, label %bb.1, label %bb.2
|
||||
|
||||
bb.1:
|
||||
; Use the alloca outside of the defining block.
|
||||
store i32 0, i32 addrspace(5)* %gep0
|
||||
store i32 1, i32 addrspace(5)* %gep1
|
||||
%gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
|
||||
%load = load i32, i32 addrspace(5)* %gep2
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%add = add i32 %load, %tid
|
||||
store i32 %add, i32 addrspace(1)* %out
|
||||
br label %bb.2
|
||||
|
||||
bb.2:
|
||||
store volatile i32 0, i32 addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @func_non_entry_block_static_alloca_align64(i32 addrspace(1)* %out, i32 %arg.cond, i32 %in) {
|
||||
; GCN-LABEL: func_non_entry_block_static_alloca_align64:
|
||||
; GCN: ; %bb.0: ; %entry
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-NEXT: s_add_u32 s4, s32, 0xfc0
|
||||
; GCN-NEXT: s_mov_b32 s7, s33
|
||||
; GCN-NEXT: s_and_b32 s33, s4, 0xfffff000
|
||||
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
|
||||
; GCN-NEXT: s_add_u32 s32, s32, 0x2000
|
||||
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; GCN-NEXT: s_cbranch_execz BB3_2
|
||||
; GCN-NEXT: ; %bb.1: ; %bb.0
|
||||
; GCN-NEXT: s_add_i32 s6, s32, 0x1000
|
||||
; GCN-NEXT: s_andn2_b32 s6, s6, 63
|
||||
; GCN-NEXT: v_mov_b32_e32 v2, 0
|
||||
; GCN-NEXT: v_mov_b32_e32 v5, s6
|
||||
; GCN-NEXT: v_mov_b32_e32 v6, 1
|
||||
; GCN-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen
|
||||
; GCN-NEXT: buffer_store_dword v6, v5, s[0:3], 0 offen offset:4
|
||||
; GCN-NEXT: v_lshl_add_u32 v2, v3, 2, s6
|
||||
; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
|
||||
; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v4
|
||||
; GCN-NEXT: s_mov_b32 s32, s6
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: v_add_u32_e32 v2, v2, v3
|
||||
; GCN-NEXT: global_store_dword v[0:1], v2, off
|
||||
; GCN-NEXT: BB3_2: ; %bb.1
|
||||
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
|
||||
; GCN-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GCN-NEXT: global_store_dword v[0:1], v0, off
|
||||
; GCN-NEXT: s_sub_u32 s32, s32, 0x2000
|
||||
; GCN-NEXT: s_mov_b32 s33, s7
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: s_setpc_b64 s[30:31]
|
||||
entry:
|
||||
%cond = icmp eq i32 %arg.cond, 0
|
||||
br i1 %cond, label %bb.0, label %bb.1
|
||||
|
||||
bb.0:
|
||||
%alloca = alloca [16 x i32], align 64, addrspace(5)
|
||||
%gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
|
||||
%gep1 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 1
|
||||
store i32 0, i32 addrspace(5)* %gep0
|
||||
store i32 1, i32 addrspace(5)* %gep1
|
||||
%gep2 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %in
|
||||
%load = load i32, i32 addrspace(5)* %gep2
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%add = add i32 %load, %tid
|
||||
store i32 %add, i32 addrspace(1)* %out
|
||||
br label %bb.1
|
||||
|
||||
bb.1:
|
||||
store volatile i32 0, i32 addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
||||
|
||||
attributes #0 = { nounwind readnone speculatable }
|
||||
Loading…
Reference in New Issue