forked from OSchip/llvm-project
Remove the code that emits MIPS' .cprestore directive.
llvm-svn: 157493
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4d9b017ef2
commit
5de59266cd
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@ -112,28 +112,6 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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return;
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}
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case Mips::CPRESTORE: {
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const MachineOperand &MO = MI->getOperand(0);
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assert(MO.isImm() && "CPRESTORE's operand must be an immediate.");
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int64_t Offset = MO.getImm();
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if (OutStreamer.hasRawTextSupport()) {
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if (!isInt<16>(Offset)) {
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EmitInstrWithMacroNoAT(MI);
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return;
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}
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} else {
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MCInstLowering.LowerCPRESTORE(Offset, MCInsts);
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for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
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I != MCInsts.end(); ++I)
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OutStreamer.EmitInstruction(*I);
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return;
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}
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break;
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}
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default:
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break;
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}
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@ -140,33 +140,6 @@ void MipsMCInstLower::LowerCPLOAD(SmallVector<MCInst, 4>& MCInsts) {
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CreateMCInst(MCInsts[2], Mips::ADDu, GPReg, GPReg, T9Reg);
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}
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// Lower ".cprestore offset" to "sw $gp, offset($sp)".
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void MipsMCInstLower::LowerCPRESTORE(int64_t Offset,
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SmallVector<MCInst, 4>& MCInsts) {
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assert(isInt<32>(Offset) && (Offset >= 0) &&
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"Imm operand of .cprestore must be a non-negative 32-bit value.");
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MCOperand SPReg = MCOperand::CreateReg(Mips::SP), BaseReg = SPReg;
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MCOperand GPReg = MCOperand::CreateReg(Mips::GP);
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if (!isInt<16>(Offset)) {
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unsigned Hi = ((Offset + 0x8000) >> 16) & 0xffff;
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Offset &= 0xffff;
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MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
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BaseReg = ATReg;
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// lui at,hi
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// addu at,at,sp
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MCInsts.resize(2);
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CreateMCInst(MCInsts[0], Mips::LUi, ATReg, MCOperand::CreateImm(Hi));
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CreateMCInst(MCInsts[1], Mips::ADDu, ATReg, ATReg, SPReg);
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}
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MCInst Sw;
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CreateMCInst(Sw, Mips::SW, GPReg, BaseReg, MCOperand::CreateImm(Offset));
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MCInsts.push_back(Sw);
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}
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MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO,
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unsigned offset) const {
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MachineOperandType MOTy = MO.getType();
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@ -34,7 +34,6 @@ public:
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void Initialize(Mangler *mang, MCContext* C);
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void Lower(const MachineInstr *MI, MCInst &OutMI) const;
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void LowerCPLOAD(SmallVector<MCInst, 4>& MCInsts);
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void LowerCPRESTORE(int64_t Offset, SmallVector<MCInst, 4>& MCInsts);
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void LowerUnalignedLoadStore(const MachineInstr *MI,
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SmallVector<MCInst, 4>& MCInsts);
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void LowerSETGP01(SmallVector<MCInst, 4>& MCInsts);
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