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AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors 

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D16863

llvm-svn: 259897
This commit is contained in:
Tom Stellard 2016-02-05 18:29:17 +00:00
parent 6da9115e53
commit 5dde1d2eb3
2 changed files with 10 additions and 10 deletions
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8
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View File

@ -124,20 +124,20 @@ AMDGPUTargetMachine::~AMDGPUTargetMachine() { }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT, R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
StringRef FS, StringRef CPU, StringRef CPU, StringRef FS,
TargetOptions Options, Reloc::Model RM, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL) CodeModel::Model CM, CodeGenOpt::Level OL)
: AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {} : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// GCN Target Machine (SI+) // GCN Target Machine (SI+)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT, GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
StringRef FS, StringRef CPU, StringRef CPU, StringRef FS,
TargetOptions Options, Reloc::Model RM, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL) CodeModel::Model CM, CodeGenOpt::Level OL)
: AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {} : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// AMDGPU Pass Setup // AMDGPU Pass Setup

12
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
View File

@ -37,8 +37,8 @@ protected:
AMDGPUIntrinsicInfo IntrinsicInfo; AMDGPUIntrinsicInfo IntrinsicInfo;
public: public:
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef FS, AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef FS, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
~AMDGPUTargetMachine(); ~AMDGPUTargetMachine();
@ -63,8 +63,8 @@ public:
class R600TargetMachine : public AMDGPUTargetMachine { class R600TargetMachine : public AMDGPUTargetMachine {
public: public:
R600TargetMachine(const Target &T, const Triple &TT, StringRef FS, R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef FS, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
@ -77,8 +77,8 @@ public:
class GCNTargetMachine : public AMDGPUTargetMachine { class GCNTargetMachine : public AMDGPUTargetMachine {
public: public:
GCNTargetMachine(const Target &T, const Triple &TT, StringRef FS, GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef FS, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override;