forked from OSchip/llvm-project
[X86] EltsFromConsecutiveLoads - clean up element size calcs. NFCI.
Determine the element/load size calculations earlier and assert that they are whole bytes in size. llvm-svn: 365674
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@ -7567,6 +7567,10 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
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"Register/Memory size mismatch");
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LoadSDNode *LDBase = Loads[FirstLoadedElt];
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assert(LDBase && "Did not find base load for merging consecutive loads");
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unsigned BaseSizeInBits = EltBaseVT.getStoreSizeInBits();
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unsigned BaseSizeInBytes = BaseSizeInBits / 8;
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int LoadSizeInBits = (1 + LastLoadedElt - FirstLoadedElt) * BaseSizeInBits;
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assert((BaseSizeInBits % 8) == 0 && "Sub-byte element loads detected");
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// Consecutive loads can contain UNDEFS but not ZERO elements.
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// Consecutive loads with UNDEFs and ZEROs elements require a
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@ -7576,9 +7580,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
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for (int i = FirstLoadedElt + 1; i <= LastLoadedElt; ++i) {
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if (LoadMask[i]) {
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SDValue Elt = peekThroughBitcasts(Elts[i]);
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LoadSDNode *LD = Loads[i];
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if (!DAG.areNonVolatileConsecutiveLoads(
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LD, LDBase, Elt.getValueType().getStoreSizeInBits() / 8,
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if (!DAG.areNonVolatileConsecutiveLoads(Loads[i], LDBase, BaseSizeInBytes,
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i - FirstLoadedElt)) {
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IsConsecutiveLoad = false;
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IsConsecutiveLoadWithZeros = false;
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@ -7646,9 +7648,6 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
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}
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}
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unsigned BaseSize = EltBaseVT.getStoreSizeInBits();
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int LoadSize = (1 + LastLoadedElt - FirstLoadedElt) * BaseSize;
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// If the upper half of a ymm/zmm load is undef then just load the lower half.
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if (VT.is256BitVector() || VT.is512BitVector()) {
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unsigned HalfNumElems = NumElems / 2;
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@ -7666,11 +7665,11 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
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// VZEXT_LOAD - consecutive 32/64-bit load/undefs followed by zeros/undefs.
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if (IsConsecutiveLoad && FirstLoadedElt == 0 &&
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(LoadSize == 32 || LoadSize == 64) &&
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(LoadSizeInBits == 32 || LoadSizeInBits == 64) &&
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((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()))) {
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MVT VecSVT = VT.isFloatingPoint() ? MVT::getFloatingPointVT(LoadSize)
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: MVT::getIntegerVT(LoadSize);
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MVT VecVT = MVT::getVectorVT(VecSVT, VT.getSizeInBits() / LoadSize);
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MVT VecSVT = VT.isFloatingPoint() ? MVT::getFloatingPointVT(LoadSizeInBits)
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: MVT::getIntegerVT(LoadSizeInBits);
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MVT VecVT = MVT::getVectorVT(VecSVT, VT.getSizeInBits() / LoadSizeInBits);
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if (TLI.isTypeLegal(VecVT)) {
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SDVTList Tys = DAG.getVTList(VecVT, MVT::Other);
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SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
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@ -7688,11 +7687,10 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
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// BROADCAST - match the smallest possible repetition pattern, load that
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// scalar/subvector element and then broadcast to the entire vector.
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if (ZeroMask.isNullValue() && isPowerOf2_32(NumElems) &&
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(BaseSize % 8) == 0 && Subtarget.hasAVX() &&
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if (ZeroMask.isNullValue() && isPowerOf2_32(NumElems) && Subtarget.hasAVX() &&
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(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector())) {
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for (unsigned SubElems = 1; SubElems < NumElems; SubElems *= 2) {
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unsigned RepeatSize = SubElems * BaseSize;
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unsigned RepeatSize = SubElems * BaseSizeInBits;
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unsigned ScalarSize = std::min(RepeatSize, 64u);
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if (!Subtarget.hasAVX2() && ScalarSize < 32)
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continue;
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