forked from OSchip/llvm-project
[AArch64][GlobalISel] Fold 64-bit cmps with 64-bit adds
G_ICMP is selected to an arithmetic overflow op (ADDS/SUBS/etc) with a dead destination + a CSINC instruction. We have a fold which allows us to combine 32-bit adds with G_ICMP. The problem with G_ICMP is that we model it as always having a 32-bit destination even though it can be a 64-bit operation. So, we were missing some opportunities for 64-bit folds. This patch teaches the fold to recognize 64-bit G_ICMPs + refactors some of the code surrounding CSINC accordingly. (Later down the line, I think we should probably change the way we handle G_ICMP in general.) Differential Revision: https://reviews.llvm.org/D111088
This commit is contained in:
Jessica Paquette
parent
2ba572a82a
commit
5dc339d982
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@ -276,13 +276,9 @@ private:
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const RegisterBank &DstRB, LLT ScalarTy,
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Register VecReg, unsigned LaneIdx,
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MachineIRBuilder &MIRBuilder) const;
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/// Emit a CSet for an integer compare.
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///
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/// \p DefReg and \p SrcReg are expected to be 32-bit scalar registers.
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MachineInstr *emitCSetForICMP(Register DefReg, unsigned Pred,
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MachineIRBuilder &MIRBuilder,
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Register SrcReg = AArch64::WZR) const;
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MachineInstr *emitCSINC(Register Dst, Register Src1, Register Src2,
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AArch64CC::CondCode Pred,
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MachineIRBuilder &MIRBuilder) const;
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/// Emit a CSet for a FP compare.
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///
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/// \p Dst is expected to be a 32-bit scalar register.
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@ -2213,27 +2209,55 @@ bool AArch64InstructionSelector::earlySelect(MachineInstr &I) {
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// fold the add into the cset for the cmp by using cinc.
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//
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// FIXME: This would probably be a lot nicer in PostLegalizerLowering.
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Register X = I.getOperand(1).getReg();
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// Only handle scalars. Scalar G_ICMP is only legal for s32, so bail out
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// early if we see it.
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LLT Ty = MRI.getType(X);
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if (Ty.isVector() || Ty.getSizeInBits() != 32)
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Register AddDst = I.getOperand(0).getReg();
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Register AddLHS = I.getOperand(1).getReg();
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Register AddRHS = I.getOperand(2).getReg();
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// Only handle scalars.
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LLT Ty = MRI.getType(AddLHS);
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if (Ty.isVector())
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return false;
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Register CmpReg = I.getOperand(2).getReg();
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MachineInstr *Cmp = getOpcodeDef(TargetOpcode::G_ICMP, CmpReg, MRI);
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// Since G_ICMP is modeled as ADDS/SUBS/ANDS, we can handle 32 bits or 64
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// bits.
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unsigned Size = Ty.getSizeInBits();
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if (Size != 32 && Size != 64)
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return false;
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auto MatchCmp = [&](Register Reg) -> MachineInstr * {
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if (!MRI.hasOneNonDBGUse(Reg))
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return nullptr;
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// If the LHS of the add is 32 bits, then we want to fold a 32-bit
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// compare.
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if (Size == 32)
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return getOpcodeDef(TargetOpcode::G_ICMP, Reg, MRI);
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// We model scalar compares using 32-bit destinations right now.
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// If it's a 64-bit compare, it'll have 64-bit sources.
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Register ZExt;
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if (!mi_match(Reg, MRI,
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m_OneNonDBGUse(m_GZExt(m_OneNonDBGUse(m_Reg(ZExt))))))
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return nullptr;
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auto *Cmp = getOpcodeDef(TargetOpcode::G_ICMP, ZExt, MRI);
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if (!Cmp ||
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MRI.getType(Cmp->getOperand(2).getReg()).getSizeInBits() != 64)
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return nullptr;
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return Cmp;
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};
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// Try to match
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// z + (cmp pred, x, y)
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MachineInstr *Cmp = MatchCmp(AddRHS);
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if (!Cmp) {
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std::swap(X, CmpReg);
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Cmp = getOpcodeDef(TargetOpcode::G_ICMP, CmpReg, MRI);
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// (cmp pred, x, y) + z
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std::swap(AddLHS, AddRHS);
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Cmp = MatchCmp(AddRHS);
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if (!Cmp)
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return false;
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}
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auto Pred =
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static_cast<CmpInst::Predicate>(Cmp->getOperand(1).getPredicate());
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emitIntegerCompare(Cmp->getOperand(2), Cmp->getOperand(3),
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Cmp->getOperand(1), MIB);
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emitCSetForICMP(I.getOperand(0).getReg(), Pred, MIB, X);
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auto &PredOp = Cmp->getOperand(1);
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auto Pred = static_cast<CmpInst::Predicate>(PredOp.getPredicate());
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const AArch64CC::CondCode InvCC =
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changeICMPPredToAArch64CC(CmpInst::getInversePredicate(Pred));
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MIB.setInstrAndDebugLoc(I);
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emitIntegerCompare(/*LHS=*/Cmp->getOperand(2),
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/*RHS=*/Cmp->getOperand(3), PredOp, MIB);
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emitCSINC(/*Dst=*/AddDst, /*Src =*/AddLHS, /*Src2=*/AddLHS, InvCC, MIB);
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I.eraseFromParent();
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return true;
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}
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@ -2963,10 +2987,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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// false, so to get the increment when it's true, we need to use the
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// inverse. In this case, we want to increment when carry is set.
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Register ZReg = AArch64::WZR;
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auto CsetMI = MIB.buildInstr(AArch64::CSINCWr, {I.getOperand(1).getReg()},
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{ZReg, ZReg})
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.addImm(getInvertedCondCode(OpAndCC.second));
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constrainSelectedInstRegOperands(*CsetMI, TII, TRI, RBI);
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emitCSINC(/*Dst=*/I.getOperand(1).getReg(), /*Src1=*/ZReg, /*Src2=*/ZReg,
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getInvertedCondCode(OpAndCC.second), MIB);
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I.eraseFromParent();
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return true;
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}
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@ -3303,9 +3325,11 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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}
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auto Pred = static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate());
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emitIntegerCompare(I.getOperand(2), I.getOperand(3), I.getOperand(1),
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MIB);
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emitCSetForICMP(I.getOperand(0).getReg(), Pred, MIB);
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const AArch64CC::CondCode InvCC =
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changeICMPPredToAArch64CC(CmpInst::getInversePredicate(Pred));
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emitIntegerCompare(I.getOperand(2), I.getOperand(3), I.getOperand(1), MIB);
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emitCSINC(/*Dst=*/I.getOperand(0).getReg(), /*Src1=*/AArch64::WZR,
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/*Src2=*/AArch64::WZR, InvCC, MIB);
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I.eraseFromParent();
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return true;
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}
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@ -4451,25 +4475,19 @@ MachineInstr *AArch64InstructionSelector::emitCSetForFCmp(
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assert(!Ty.isVector() && Ty.getSizeInBits() == 32 &&
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"Expected a 32-bit scalar register?");
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#endif
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const Register ZeroReg = AArch64::WZR;
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auto EmitCSet = [&](Register CsetDst, AArch64CC::CondCode CC) {
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auto CSet =
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MIRBuilder.buildInstr(AArch64::CSINCWr, {CsetDst}, {ZeroReg, ZeroReg})
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.addImm(getInvertedCondCode(CC));
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constrainSelectedInstRegOperands(*CSet, TII, TRI, RBI);
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return &*CSet;
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};
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const Register ZReg = AArch64::WZR;
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AArch64CC::CondCode CC1, CC2;
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changeFCMPPredToAArch64CC(Pred, CC1, CC2);
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auto InvCC1 = AArch64CC::getInvertedCondCode(CC1);
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if (CC2 == AArch64CC::AL)
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return EmitCSet(Dst, CC1);
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return emitCSINC(/*Dst=*/Dst, /*Src1=*/ZReg, /*Src2=*/ZReg, InvCC1,
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MIRBuilder);
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const TargetRegisterClass *RC = &AArch64::GPR32RegClass;
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Register Def1Reg = MRI.createVirtualRegister(RC);
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Register Def2Reg = MRI.createVirtualRegister(RC);
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EmitCSet(Def1Reg, CC1);
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EmitCSet(Def2Reg, CC2);
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auto InvCC2 = AArch64CC::getInvertedCondCode(CC2);
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emitCSINC(/*Dst=*/Def1Reg, /*Src1=*/ZReg, /*Src2=*/ZReg, InvCC1, MIRBuilder);
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emitCSINC(/*Dst=*/Def2Reg, /*Src1=*/ZReg, /*Src2=*/ZReg, InvCC2, MIRBuilder);
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auto OrMI = MIRBuilder.buildInstr(AArch64::ORRWrr, {Dst}, {Def1Reg, Def2Reg});
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constrainSelectedInstRegOperands(*OrMI, TII, TRI, RBI);
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return &*OrMI;
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@ -4578,16 +4596,25 @@ MachineInstr *AArch64InstructionSelector::emitVectorConcat(
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}
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MachineInstr *
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AArch64InstructionSelector::emitCSetForICMP(Register DefReg, unsigned Pred,
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MachineIRBuilder &MIRBuilder,
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Register SrcReg) const {
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// CSINC increments the result when the predicate is false. Invert it.
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const AArch64CC::CondCode InvCC = changeICMPPredToAArch64CC(
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CmpInst::getInversePredicate((CmpInst::Predicate)Pred));
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auto I = MIRBuilder.buildInstr(AArch64::CSINCWr, {DefReg}, {SrcReg, SrcReg})
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.addImm(InvCC);
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constrainSelectedInstRegOperands(*I, TII, TRI, RBI);
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return &*I;
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AArch64InstructionSelector::emitCSINC(Register Dst, Register Src1,
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Register Src2, AArch64CC::CondCode Pred,
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MachineIRBuilder &MIRBuilder) const {
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auto &MRI = *MIRBuilder.getMRI();
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const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Dst);
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// If we used a register class, then this won't necessarily have an LLT.
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// Compute the size based off whether or not we have a class or bank.
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unsigned Size;
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if (const auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
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Size = TRI.getRegSizeInBits(*RC);
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else
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Size = MRI.getType(Dst).getSizeInBits();
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// Some opcodes use s1.
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assert(Size <= 64 && "Expected 64 bits or less only!");
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static const unsigned OpcTable[2] = {AArch64::CSINCWr, AArch64::CSINCXr};
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unsigned Opc = OpcTable[Size == 64];
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auto CSINC = MIRBuilder.buildInstr(Opc, {Dst}, {Src1, Src2}).addImm(Pred);
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constrainSelectedInstRegOperands(*CSINC, TII, TRI, RBI);
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return &*CSINC;
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}
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std::pair<MachineInstr *, AArch64CC::CondCode>
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@ -11,11 +11,12 @@ body: |
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; CHECK-LABEL: name: cmp_imm_32
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: $w0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
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; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = G_CONSTANT i32 42
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%5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %1
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@ -34,11 +35,12 @@ body: |
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; CHECK-LABEL: name: cmp_imm_64
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 42, 0, implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: $w0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 42, 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 42
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%5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1
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@ -57,13 +59,14 @@ body: |
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; CHECK-LABEL: name: cmp_imm_out_of_range
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 13132
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBREG_TO_REG]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: $w0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 13132
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBREG_TO_REG]], implicit-def $nzcv
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 13132
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%5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1
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@ -81,11 +84,12 @@ body: |
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liveins: $w0
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; CHECK-LABEL: name: cmp_imm_lookthrough
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: $w0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
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; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s64) = G_CONSTANT i64 42
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%2:gpr(s32) = G_TRUNC %1(s64)
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@ -104,11 +108,12 @@ body: |
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liveins: $w0
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; CHECK-LABEL: name: cmp_imm_lookthrough_bad_trunc
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: $w0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
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; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s64) = G_CONSTANT i64 68719476736 ; 0x1000000000
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%2:gpr(s32) = G_TRUNC %1(s64) ; Value truncates to 0
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@ -127,11 +132,12 @@ body: |
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liveins: $w0
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; CHECK-LABEL: name: cmp_neg_imm_32
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; CHECK: liveins: $w0
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; CHECK: %reg0:gpr32sp = COPY $w0
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; CHECK: [[ADDSWri:%[0-9]+]]:gpr32 = ADDSWri %reg0, 10, 0, implicit-def $nzcv
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; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: $w0 = COPY %cmp
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; CHECK: RET_ReallyLR implicit $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %reg0:gpr32sp = COPY $w0
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; CHECK-NEXT: [[ADDSWri:%[0-9]+]]:gpr32 = ADDSWri %reg0, 10, 0, implicit-def $nzcv
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; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY %cmp
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%reg0:gpr(s32) = COPY $w0
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%cst:gpr(s32) = G_CONSTANT i32 -10
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%cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s32), %cst
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@ -149,11 +155,12 @@ body: |
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liveins: $x0
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; CHECK-LABEL: name: cmp_neg_imm_64
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; CHECK: liveins: $x0
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; CHECK: %reg0:gpr64sp = COPY $x0
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; CHECK: [[ADDSXri:%[0-9]+]]:gpr64 = ADDSXri %reg0, 10, 0, implicit-def $nzcv
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; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: $w0 = COPY %cmp
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; CHECK: RET_ReallyLR implicit $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
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; CHECK-NEXT: [[ADDSXri:%[0-9]+]]:gpr64 = ADDSXri %reg0, 10, 0, implicit-def $nzcv
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||||
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
|
||||
; CHECK-NEXT: $w0 = COPY %cmp
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s64) = COPY $x0
|
||||
%cst:gpr(s64) = G_CONSTANT i64 -10
|
||||
%cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s64), %cst
|
||||
|
|
@ -171,12 +178,13 @@ body: |
|
|||
liveins: $w0
|
||||
; CHECK-LABEL: name: cmp_neg_imm_invalid
|
||||
; CHECK: liveins: $w0
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %cst:gpr32 = MOVi32imm -5000
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %cst, implicit-def $nzcv
|
||||
; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %cmp
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: %reg0:gpr32 = COPY $w0
|
||||
; CHECK-NEXT: %cst:gpr32 = MOVi32imm -5000
|
||||
; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %cst, implicit-def $nzcv
|
||||
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
|
||||
; CHECK-NEXT: $w0 = COPY %cmp
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%cst:gpr(s32) = G_CONSTANT i32 -5000
|
||||
%cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s32), %cst
|
||||
|
|
@ -194,12 +202,13 @@ body: |
|
|||
|
||||
; CHECK-LABEL: name: cmp_arith_extended_s64
|
||||
; CHECK: liveins: $w0, $x1
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %reg1:gpr64sp = COPY $x1
|
||||
; CHECK: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %reg1, %reg0, 18, implicit-def $nzcv
|
||||
; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %cmp
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: %reg0:gpr32 = COPY $w0
|
||||
; CHECK-NEXT: %reg1:gpr64sp = COPY $x1
|
||||
; CHECK-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %reg1, %reg0, 18, implicit-def $nzcv
|
||||
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
|
||||
; CHECK-NEXT: $w0 = COPY %cmp
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%reg1:gpr(s64) = COPY $x1
|
||||
%ext:gpr(s64) = G_ZEXT %reg0(s32)
|
||||
|
|
@ -221,14 +230,15 @@ body: |
|
|||
|
||||
; CHECK-LABEL: name: cmp_arith_extended_s32
|
||||
; CHECK: liveins: $w0, $w1, $h0
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub
|
||||
; CHECK: %reg0:gpr32all = COPY [[SUBREG_TO_REG]]
|
||||
; CHECK: %reg1:gpr32sp = COPY $w1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %reg0
|
||||
; CHECK: [[SUBSWrx:%[0-9]+]]:gpr32 = SUBSWrx %reg1, [[COPY]], 10, implicit-def $nzcv
|
||||
; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %cmp
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub
|
||||
; CHECK-NEXT: %reg0:gpr32all = COPY [[SUBREG_TO_REG]]
|
||||
; CHECK-NEXT: %reg1:gpr32sp = COPY $w1
|
||||
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %reg0
|
||||
; CHECK-NEXT: [[SUBSWrx:%[0-9]+]]:gpr32 = SUBSWrx %reg1, [[COPY]], 10, implicit-def $nzcv
|
||||
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
|
||||
; CHECK-NEXT: $w0 = COPY %cmp
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s16) = COPY $h0
|
||||
%reg1:gpr(s32) = COPY $w1
|
||||
%ext:gpr(s32) = G_ZEXT %reg0(s16)
|
||||
|
|
@ -252,14 +262,15 @@ body: |
|
|||
|
||||
; CHECK-LABEL: name: cmp_arith_extended_shl_too_large
|
||||
; CHECK: liveins: $w0, $x1
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %reg1:gpr64 = COPY $x1
|
||||
; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %reg0, 0
|
||||
; CHECK: %ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
|
||||
; CHECK: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %reg1, %ext, 5, implicit-def $nzcv
|
||||
; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %cmp
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: %reg0:gpr32 = COPY $w0
|
||||
; CHECK-NEXT: %reg1:gpr64 = COPY $x1
|
||||
; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %reg0, 0
|
||||
; CHECK-NEXT: %ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32
|
||||
; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %reg1, %ext, 5, implicit-def $nzcv
|
||||
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
|
||||
; CHECK-NEXT: $w0 = COPY %cmp
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%reg1:gpr(s64) = COPY $x1
|
||||
%ext:gpr(s64) = G_ZEXT %reg0(s32)
|
||||
|
|
@ -284,13 +295,14 @@ body: |
|
|||
|
||||
; CHECK-LABEL: name: cmp_add_rhs
|
||||
; CHECK: liveins: $w0, $w1, $w2
|
||||
; CHECK: %cmp_lhs:gpr32 = COPY $w0
|
||||
; CHECK: %cmp_rhs:gpr32 = COPY $w1
|
||||
; CHECK: %add_rhs:gpr32 = COPY $w2
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
|
||||
; CHECK: %add:gpr32 = CSINCWr %add_rhs, %add_rhs, 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %add
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: %cmp_lhs:gpr32 = COPY $w0
|
||||
; CHECK-NEXT: %cmp_rhs:gpr32 = COPY $w1
|
||||
; CHECK-NEXT: %add_rhs:gpr32 = COPY $w2
|
||||
; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
|
||||
; CHECK-NEXT: %add:gpr32 = CSINCWr %add_rhs, %add_rhs, 1, implicit $nzcv
|
||||
; CHECK-NEXT: $w0 = COPY %add
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
||||
%cmp_lhs:gpr(s32) = COPY $w0
|
||||
%cmp_rhs:gpr(s32) = COPY $w1
|
||||
%add_rhs:gpr(s32) = COPY $w2
|
||||
|
|
@ -314,13 +326,14 @@ body: |
|
|||
|
||||
; CHECK-LABEL: name: cmp_add_lhs
|
||||
; CHECK: liveins: $w0, $w1, $w2
|
||||
; CHECK: %cmp_lhs:gpr32 = COPY $w0
|
||||
; CHECK: %cmp_rhs:gpr32 = COPY $w1
|
||||
; CHECK: %add_lhs:gpr32 = COPY $w2
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
|
||||
; CHECK: %add:gpr32 = CSINCWr %add_lhs, %add_lhs, 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %add
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: %cmp_lhs:gpr32 = COPY $w0
|
||||
; CHECK-NEXT: %cmp_rhs:gpr32 = COPY $w1
|
||||
; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2
|
||||
; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
|
||||
; CHECK-NEXT: %add:gpr32 = CSINCWr %add_lhs, %add_lhs, 1, implicit $nzcv
|
||||
; CHECK-NEXT: $w0 = COPY %add
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $w0
|
||||
%cmp_lhs:gpr(s32) = COPY $w0
|
||||
%cmp_rhs:gpr(s32) = COPY $w1
|
||||
%add_lhs:gpr(s32) = COPY $w2
|
||||
|
|
@ -344,13 +357,14 @@ body: |
|
|||
|
||||
; CHECK-LABEL: name: cmp_add_lhs_vector
|
||||
; CHECK: liveins: $q0, $q1, $q2
|
||||
; CHECK: %cmp_lhs:fpr128 = COPY $q0
|
||||
; CHECK: %cmp_rhs:fpr128 = COPY $q1
|
||||
; CHECK: %add_lhs:fpr128 = COPY $q2
|
||||
; CHECK: [[CMEQv4i32_:%[0-9]+]]:fpr128 = CMEQv4i32 %cmp_lhs, %cmp_rhs
|
||||
; CHECK: %add:fpr128 = ADDv4i32 %add_lhs, [[CMEQv4i32_]]
|
||||
; CHECK: $q0 = COPY %add
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: %cmp_lhs:fpr128 = COPY $q0
|
||||
; CHECK-NEXT: %cmp_rhs:fpr128 = COPY $q1
|
||||
; CHECK-NEXT: %add_lhs:fpr128 = COPY $q2
|
||||
; CHECK-NEXT: [[CMEQv4i32_:%[0-9]+]]:fpr128 = CMEQv4i32 %cmp_lhs, %cmp_rhs
|
||||
; CHECK-NEXT: %add:fpr128 = ADDv4i32 %add_lhs, [[CMEQv4i32_]]
|
||||
; CHECK-NEXT: $q0 = COPY %add
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
||||
%cmp_lhs:fpr(<4 x s32>) = COPY $q0
|
||||
%cmp_rhs:fpr(<4 x s32>) = COPY $q1
|
||||
%add_lhs:fpr(<4 x s32>) = COPY $q2
|
||||
|
|
@ -358,3 +372,108 @@ body: |
|
|||
%add:fpr(<4 x s32>) = G_ADD %add_lhs, %cmp
|
||||
$q0 = COPY %add(<4 x s32>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
---
|
||||
name: cmp_add_rhs_64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0, $x1, $x2
|
||||
|
||||
; The CSINC should use the add's RHS.
|
||||
; CHECK-LABEL: name: cmp_add_rhs_64
|
||||
; CHECK: liveins: $x0, $x1, $x2
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0
|
||||
; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1
|
||||
; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2
|
||||
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
|
||||
; CHECK-NEXT: %add:gpr64 = CSINCXr %add_rhs, %add_rhs, 1, implicit $nzcv
|
||||
; CHECK-NEXT: $x0 = COPY %add
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
||||
%cmp_lhs:gpr(s64) = COPY $x0
|
||||
%cmp_rhs:gpr(s64) = COPY $x1
|
||||
%add_rhs:gpr(s64) = COPY $x2
|
||||
%cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
|
||||
%cmp_ext:gpr(s64) = G_ZEXT %cmp
|
||||
%add:gpr(s64) = G_ADD %cmp_ext, %add_rhs
|
||||
$x0 = COPY %add(s64)
|
||||
RET_ReallyLR implicit $x0
|
||||
|
||||
...
|
||||
---
|
||||
name: cmp_add_rhs_64_zext_multi_use
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0, $x1, $x2
|
||||
|
||||
; The ZExt is used more than once so don't fold.
|
||||
; CHECK-LABEL: name: cmp_add_rhs_64_zext_multi_use
|
||||
; CHECK: liveins: $x0, $x1, $x2
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0
|
||||
; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1
|
||||
; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2
|
||||
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
|
||||
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
|
||||
; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG 0, %cmp, %subreg.sub_32
|
||||
; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs
|
||||
; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext
|
||||
; CHECK-NEXT: $x0 = COPY %or
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
||||
%cmp_lhs:gpr(s64) = COPY $x0
|
||||
%cmp_rhs:gpr(s64) = COPY $x1
|
||||
%add_rhs:gpr(s64) = COPY $x2
|
||||
%cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
|
||||
%cmp_ext:gpr(s64) = G_ZEXT %cmp
|
||||
%add:gpr(s64) = G_ADD %cmp_ext, %add_rhs
|
||||
%or:gpr(s64) = G_OR %add, %cmp_ext
|
||||
$x0 = COPY %or(s64)
|
||||
RET_ReallyLR implicit $x0
|
||||
|
||||
...
|
||||
---
|
||||
name: cmp_add_rhs_64_cmp_multi_use
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0, $x1, $x2
|
||||
|
||||
; The cmp is used more than once so don't fold.
|
||||
; CHECK-LABEL: name: cmp_add_rhs_64_cmp_multi_use
|
||||
; CHECK: liveins: $x0, $x1, $x2
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0
|
||||
; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1
|
||||
; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2
|
||||
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
|
||||
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
|
||||
; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG 0, %cmp, %subreg.sub_32
|
||||
; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], %cmp, %subreg.sub_32
|
||||
; CHECK-NEXT: %cmp_ext2:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31
|
||||
; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext2
|
||||
; CHECK-NEXT: $x0 = COPY %or
|
||||
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
||||
%cmp_lhs:gpr(s64) = COPY $x0
|
||||
%cmp_rhs:gpr(s64) = COPY $x1
|
||||
%add_rhs:gpr(s64) = COPY $x2
|
||||
%cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs
|
||||
%cmp_ext:gpr(s64) = G_ZEXT %cmp
|
||||
%add:gpr(s64) = G_ADD %cmp_ext, %add_rhs
|
||||
%cmp_ext2:gpr(s64) = G_SEXT %cmp
|
||||
%or:gpr(s64) = G_OR %add, %cmp_ext2
|
||||
$x0 = COPY %or(s64)
|
||||
RET_ReallyLR implicit $x0
|
||||
|
|
|
|||
Loading…
Reference in New Issue