forked from OSchip/llvm-project
[MIPS GlobalISel] Select branch instructions
Select G_BR and G_BRCOND for MIPS32. Unconditional branch G_BR does not have register operand, for that reason we only add tests. Since conditional branch G_BRCOND compares register to zero on MIPS32, explicit extension must be performed on i1 condition in order to set high bits to appropriate value. Differential Revision: https://reviews.llvm.org/D58182 llvm-svn: 354022
This commit is contained in:
Petar Avramovic
parent
24383cd7bb
commit
5d9b8eed85
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@ -1176,7 +1176,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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}
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case TargetOpcode::G_BRCOND:
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Observer.changingInstr(MI);
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widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ANYEXT);
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widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
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Observer.changedInstr(MI);
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return Legalized;
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@ -153,6 +153,13 @@ bool MipsInstructionSelector::select(MachineInstr &I,
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.addImm(0);
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break;
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}
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case G_BRCOND: {
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE))
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.add(I.getOperand(0))
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.addUse(Mips::ZERO)
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.add(I.getOperand(1));
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break;
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}
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case G_STORE:
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case G_LOAD:
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case G_ZEXTLOAD:
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@ -52,6 +52,10 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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.minScalar(0, s32)
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.minScalar(1, s32);
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getActionDefinitionsBuilder(G_BRCOND)
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.legalFor({s32})
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.minScalar(0, s32);
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getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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@ -106,6 +106,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case G_CONSTANT:
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case G_FRAME_INDEX:
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case G_GLOBAL_VALUE:
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case G_BRCOND:
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OperandsMapping =
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getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
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break;
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@ -0,0 +1,105 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define i32 @Unconditional_branch(i32 %a, i32 %b) {
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entry:
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br label %block
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end: ; preds = %block
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ret i32 %a
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block: ; preds = %entry
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br label %end
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}
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define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
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br i1 %cond, label %if.then, label %if.else
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if.then: ; preds = %0
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ret i32 %a
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if.else: ; preds = %0
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ret i32 %b
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}
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...
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---
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name: Unconditional_branch
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; MIPS32-LABEL: name: Unconditional_branch
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; MIPS32: bb.0.entry:
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; MIPS32: successors: %bb.2(0x80000000)
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: J %bb.2, implicit-def $at
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; MIPS32: bb.1.end:
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; MIPS32: $v0 = COPY [[COPY]]
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; MIPS32: RetRA implicit $v0
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; MIPS32: bb.2.block:
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; MIPS32: successors: %bb.1(0x80000000)
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; MIPS32: J %bb.1, implicit-def $at
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bb.1.entry:
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liveins: $a0, $a1
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%0:gprb(s32) = COPY $a0
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G_BR %bb.3
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bb.2.end:
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$v0 = COPY %0(s32)
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RetRA implicit $v0
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bb.3.block:
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G_BR %bb.2
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...
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---
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name: Conditional_branch
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; MIPS32-LABEL: name: Conditional_branch
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; MIPS32: bb.0 (%ir-block.0):
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; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
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; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
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; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
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; MIPS32: BNE [[AND]], $zero, %bb.1, implicit-def $at
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; MIPS32: J %bb.2, implicit-def $at
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; MIPS32: bb.1.if.then:
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; MIPS32: $v0 = COPY [[COPY1]]
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; MIPS32: RetRA implicit $v0
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; MIPS32: bb.2.if.else:
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; MIPS32: $v0 = COPY [[COPY2]]
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; MIPS32: RetRA implicit $v0
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bb.1 (%ir-block.0):
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liveins: $a0, $a1, $a2
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%3:gprb(s32) = COPY $a0
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%1:gprb(s32) = COPY $a1
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%2:gprb(s32) = COPY $a2
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%5:gprb(s32) = G_CONSTANT i32 1
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%6:gprb(s32) = COPY %3(s32)
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%4:gprb(s32) = G_AND %6, %5
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G_BRCOND %4(s32), %bb.2
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G_BR %bb.3
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bb.2.if.then:
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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bb.3.if.else:
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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@ -0,0 +1,100 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define i32 @Unconditional_branch(i32 %a, i32 %b) {
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entry:
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br label %block
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end: ; preds = %block
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ret i32 %a
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block: ; preds = %entry
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br label %end
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}
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define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
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br i1 %cond, label %if.then, label %if.else
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if.then: ; preds = %0
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ret i32 %a
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if.else: ; preds = %0
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ret i32 %b
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}
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...
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---
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name: Unconditional_branch
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alignment: 2
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tracksRegLiveness: true
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body: |
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; MIPS32-LABEL: name: Unconditional_branch
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; MIPS32: bb.0.entry:
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; MIPS32: successors: %bb.2(0x80000000)
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: G_BR %bb.2
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; MIPS32: bb.1.end:
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; MIPS32: $v0 = COPY [[COPY]](s32)
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; MIPS32: RetRA implicit $v0
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; MIPS32: bb.2.block:
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; MIPS32: successors: %bb.1(0x80000000)
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; MIPS32: G_BR %bb.1
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bb.1.entry:
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liveins: $a0, $a1
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%0:_(s32) = COPY $a0
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G_BR %bb.3
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bb.2.end:
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$v0 = COPY %0(s32)
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RetRA implicit $v0
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bb.3.block:
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G_BR %bb.2
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...
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---
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name: Conditional_branch
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alignment: 2
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tracksRegLiveness: true
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body: |
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; MIPS32-LABEL: name: Conditional_branch
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; MIPS32: bb.0 (%ir-block.0):
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; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
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; MIPS32: G_BRCOND [[AND]](s32), %bb.1
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; MIPS32: G_BR %bb.2
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; MIPS32: bb.1.if.then:
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; MIPS32: $v0 = COPY [[COPY1]](s32)
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; MIPS32: RetRA implicit $v0
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; MIPS32: bb.2.if.else:
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; MIPS32: $v0 = COPY [[COPY2]](s32)
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; MIPS32: RetRA implicit $v0
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bb.1 (%ir-block.0):
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liveins: $a0, $a1, $a2
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%3:_(s32) = COPY $a0
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%0:_(s1) = G_TRUNC %3(s32)
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%1:_(s32) = COPY $a1
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%2:_(s32) = COPY $a2
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G_BRCOND %0(s1), %bb.2
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G_BR %bb.3
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bb.2.if.then:
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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bb.3.if.else:
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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@ -0,0 +1,58 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
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define i32 @Unconditional_branch(i32 %a, i32 %b) {
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; MIPS32-LABEL: Unconditional_branch:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: addiu $sp, $sp, -8
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; MIPS32-NEXT: .cfi_def_cfa_offset 8
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; MIPS32-NEXT: sw $4, 4($sp) # 4-byte Folded Spill
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; MIPS32-NEXT: j $BB0_2
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; MIPS32-NEXT: nop
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; MIPS32-NEXT: $BB0_1: # %end
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; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
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; MIPS32-NEXT: addiu $sp, $sp, 8
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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; MIPS32-NEXT: $BB0_2: # %block
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; MIPS32-NEXT: j $BB0_1
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; MIPS32-NEXT: nop
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entry:
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br label %block
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ret i32 %b
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end:
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ret i32 %a
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block:
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br label %end
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}
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define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
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; MIPS32-LABEL: Conditional_branch:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: addiu $sp, $sp, -8
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; MIPS32-NEXT: .cfi_def_cfa_offset 8
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; MIPS32-NEXT: lui $1, 0
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; MIPS32-NEXT: ori $1, $1, 1
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; MIPS32-NEXT: and $1, $4, $1
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; MIPS32-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
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; MIPS32-NEXT: sw $6, 0($sp) # 4-byte Folded Spill
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; MIPS32-NEXT: bnez $1, $BB1_2
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; MIPS32-NEXT: nop
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; MIPS32-NEXT: # %bb.1:
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; MIPS32-NEXT: j $BB1_3
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; MIPS32-NEXT: nop
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; MIPS32-NEXT: $BB1_2: # %if.then
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; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
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; MIPS32-NEXT: addiu $sp, $sp, 8
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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; MIPS32-NEXT: $BB1_3: # %if.else
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; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
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; MIPS32-NEXT: addiu $sp, $sp, 8
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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br i1 %cond, label %if.then, label %if.else
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if.then:
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ret i32 %a
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if.else:
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ret i32 %b
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}
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@ -0,0 +1,103 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define i32 @Unconditional_branch(i32 %a, i32 %b) {
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entry:
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br label %block
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end: ; preds = %block
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ret i32 %a
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block: ; preds = %entry
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br label %end
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}
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define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
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br i1 %cond, label %if.then, label %if.else
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if.then: ; preds = %0
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ret i32 %a
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if.else: ; preds = %0
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ret i32 %b
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}
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...
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---
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name: Unconditional_branch
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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body: |
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; MIPS32-LABEL: name: Unconditional_branch
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; MIPS32: bb.0.entry:
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; MIPS32: successors: %bb.2(0x80000000)
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: G_BR %bb.2
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; MIPS32: bb.1.end:
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; MIPS32: $v0 = COPY [[COPY]](s32)
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; MIPS32: RetRA implicit $v0
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; MIPS32: bb.2.block:
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; MIPS32: successors: %bb.1(0x80000000)
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; MIPS32: G_BR %bb.1
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bb.1.entry:
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liveins: $a0, $a1
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%0:_(s32) = COPY $a0
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G_BR %bb.3
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bb.2.end:
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$v0 = COPY %0(s32)
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RetRA implicit $v0
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bb.3.block:
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G_BR %bb.2
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...
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---
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name: Conditional_branch
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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body: |
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; MIPS32-LABEL: name: Conditional_branch
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; MIPS32: bb.0 (%ir-block.0):
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; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; MIPS32: liveins: $a0, $a1, $a2
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
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; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32)
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; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]]
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; MIPS32: G_BRCOND [[AND]](s32), %bb.1
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; MIPS32: G_BR %bb.2
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; MIPS32: bb.1.if.then:
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; MIPS32: $v0 = COPY [[COPY1]](s32)
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; MIPS32: RetRA implicit $v0
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; MIPS32: bb.2.if.else:
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; MIPS32: $v0 = COPY [[COPY2]](s32)
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; MIPS32: RetRA implicit $v0
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bb.1 (%ir-block.0):
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liveins: $a0, $a1, $a2
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%3:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(s32) = COPY $a2
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%5:_(s32) = G_CONSTANT i32 1
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%6:_(s32) = COPY %3(s32)
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%4:_(s32) = G_AND %6, %5
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G_BRCOND %4(s32), %bb.2
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G_BR %bb.3
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bb.2.if.then:
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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bb.3.if.else:
|
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$v0 = COPY %2(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue