forked from OSchip/llvm-project
Added base array id's to Memory Accesses
These id's allow us to cread id -> array base value mappings. llvm-svn: 214169
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@ -183,6 +183,9 @@ public:
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/// @brief Get the base address of this access (e.g. A for A[i+j]).
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/// @brief Get the base address of this access (e.g. A for A[i+j]).
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Value *getBaseAddr() const { return BaseAddr; }
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Value *getBaseAddr() const { return BaseAddr; }
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/// @brief Get the base array isl_id for this access.
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__isl_give isl_id *getArrayId() const;
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const std::string &getBaseName() const { return BaseName; }
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const std::string &getBaseName() const { return BaseName; }
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const Instruction *getAccessInstruction() const { return Inst; }
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const Instruction *getAccessInstruction() const { return Inst; }
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@ -309,6 +309,10 @@ MemoryAccess::~MemoryAccess() {
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isl_map_free(newAccessRelation);
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isl_map_free(newAccessRelation);
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}
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}
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isl_id *MemoryAccess::getArrayId() const {
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return isl_map_get_tuple_id(AccessRelation, isl_dim_out);
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}
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isl_map *MemoryAccess::getAccessRelation() const {
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isl_map *MemoryAccess::getAccessRelation() const {
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return isl_map_copy(AccessRelation);
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return isl_map_copy(AccessRelation);
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}
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}
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@ -327,7 +331,6 @@ isl_map *MemoryAccess::getNewAccessRelation() const {
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isl_basic_map *MemoryAccess::createBasicAccessMap(ScopStmt *Statement) {
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isl_basic_map *MemoryAccess::createBasicAccessMap(ScopStmt *Statement) {
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isl_space *Space = isl_space_set_alloc(Statement->getIslCtx(), 0, 1);
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isl_space *Space = isl_space_set_alloc(Statement->getIslCtx(), 0, 1);
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Space = isl_space_set_tuple_name(Space, isl_dim_set, getBaseName().c_str());
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Space = isl_space_align_params(Space, Statement->getDomainSpace());
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Space = isl_space_align_params(Space, Statement->getDomainSpace());
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return isl_basic_map_from_domain_and_range(
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return isl_basic_map_from_domain_and_range(
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@ -399,8 +402,10 @@ MemoryAccess::MemoryAccess(const IRAccess &Access, const Instruction *AccInst,
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ScopStmt *Statement)
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ScopStmt *Statement)
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: Statement(Statement), Inst(AccInst), newAccessRelation(nullptr) {
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: Statement(Statement), Inst(AccInst), newAccessRelation(nullptr) {
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isl_ctx *Ctx = Statement->getIslCtx();
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BaseAddr = Access.getBase();
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BaseAddr = Access.getBase();
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BaseName = getIslCompatibleName("MemRef_", getBaseAddr(), "");
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BaseName = getIslCompatibleName("MemRef_", getBaseAddr(), "");
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isl_id *BaseAddrId = isl_id_alloc(Ctx, getBaseName().c_str(), nullptr);
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if (!Access.isAffine()) {
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if (!Access.isAffine()) {
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// We overapproximate non-affine accesses with a possible access to the
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// We overapproximate non-affine accesses with a possible access to the
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@ -408,14 +413,15 @@ MemoryAccess::MemoryAccess(const IRAccess &Access, const Instruction *AccInst,
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// access must or may happen. However, for write accesses it is important to
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// access must or may happen. However, for write accesses it is important to
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// differentiate between writes that must happen and writes that may happen.
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// differentiate between writes that must happen and writes that may happen.
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AccessRelation = isl_map_from_basic_map(createBasicAccessMap(Statement));
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AccessRelation = isl_map_from_basic_map(createBasicAccessMap(Statement));
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AccessRelation =
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isl_map_set_tuple_id(AccessRelation, isl_dim_out, BaseAddrId);
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Type = Access.isRead() ? READ : MAY_WRITE;
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Type = Access.isRead() ? READ : MAY_WRITE;
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return;
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return;
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}
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}
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Type = Access.isRead() ? READ : MUST_WRITE;
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Type = Access.isRead() ? READ : MUST_WRITE;
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isl_space *Space = isl_space_alloc(Statement->getIslCtx(), 0,
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isl_space *Space = isl_space_alloc(Ctx, 0, Statement->getNumIterators(), 0);
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Statement->getNumIterators(), 0);
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AccessRelation = isl_map_universe(Space);
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AccessRelation = isl_map_universe(Space);
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for (int i = 0, Size = Access.Subscripts.size(); i < Size; ++i) {
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for (int i = 0, Size = Access.Subscripts.size(); i < Size; ++i) {
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@ -431,9 +437,7 @@ MemoryAccess::MemoryAccess(const IRAccess &Access, const Instruction *AccInst,
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// two subsequent values of 'i' index two values that are stored next to
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// two subsequent values of 'i' index two values that are stored next to
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// each other in memory. By this division we make this characteristic
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// each other in memory. By this division we make this characteristic
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// obvious again.
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// obvious again.
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isl_val *v;
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isl_val *v = isl_val_int_from_si(Ctx, Access.getElemSizeInBytes());
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v = isl_val_int_from_si(isl_pw_aff_get_ctx(Affine),
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Access.getElemSizeInBytes());
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Affine = isl_pw_aff_scale_down_val(Affine, v);
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Affine = isl_pw_aff_scale_down_val(Affine, v);
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}
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}
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@ -445,10 +449,11 @@ MemoryAccess::MemoryAccess(const IRAccess &Access, const Instruction *AccInst,
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Space = Statement->getDomainSpace();
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Space = Statement->getDomainSpace();
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AccessRelation = isl_map_set_tuple_id(
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AccessRelation = isl_map_set_tuple_id(
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AccessRelation, isl_dim_in, isl_space_get_tuple_id(Space, isl_dim_set));
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AccessRelation, isl_dim_in, isl_space_get_tuple_id(Space, isl_dim_set));
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isl_space_free(Space);
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AccessRelation =
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AccessRelation = isl_map_set_tuple_name(AccessRelation, isl_dim_out,
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isl_map_set_tuple_id(AccessRelation, isl_dim_out, BaseAddrId);
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getBaseName().c_str());
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assumeNoOutOfBound(Access);
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assumeNoOutOfBound(Access);
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isl_space_free(Space);
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}
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}
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void MemoryAccess::realignParams() {
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void MemoryAccess::realignParams() {
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