forked from OSchip/llvm-project
parent
6cd144e676
commit
5d72e6cb69
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@ -28,10 +28,12 @@ class SSARegMap {
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return RegClassMap[actualReg];
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}
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void addRegMap(unsigned Reg, const TargetRegisterClass* RegClass) {
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assert(rescale(Reg) == RegClassMap.size() &&
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"Register mapping not added in sequential order!");
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/// createVirtualRegister - Create and return a new virtual register in the
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/// function with the specified register class.
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///
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unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
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RegClassMap.push_back(RegClass);
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return RegClassMap.size()+MRegisterInfo::FirstVirtualRegister-1;
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}
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};
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