forked from OSchip/llvm-project
parent
fd6f16fab9
commit
5d56769fb6
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@ -225,12 +225,12 @@ SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
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MVT::Other, Offset0, Base, Chain);
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SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
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dl, NVT), 0);
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SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPEVEN, dl,
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SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
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MVT::f64, Undef, SDValue(LD0, 0));
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SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
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MVT::Other, Offset1, Base, SDValue(LD0, 1));
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SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl,
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SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
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MVT::f64, I0, SDValue(LD1, 0));
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ReplaceUses(SDValue(N, 0), I1);
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@ -266,9 +266,9 @@ SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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// Get the even and odd part from the f64 register
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SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPODD,
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SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
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dl, MVT::f32, N1);
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SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPEVEN,
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SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
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dl, MVT::f32, N1);
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// The second store should start after for 4 bytes.
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@ -438,9 +438,9 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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SDValue Undef = SDValue(
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CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
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SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
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SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPEVEN, dl,
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SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
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MVT::f64, Undef, SDValue(MTC, 0));
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SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl,
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SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
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MVT::f64, I0, SDValue(MTC, 0));
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ReplaceUses(SDValue(Node, 0), I1);
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return I1.getNode();
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@ -23,15 +23,6 @@ class MipsSubtarget;
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class TargetInstrInfo;
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class Type;
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namespace Mips {
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/// SubregIndex - The index of various sized subregister classes. Note that
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/// these indices must be kept in sync with the class indices in the
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/// MipsRegisterInfo.td file.
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enum SubregIndex {
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SUBREG_FPEVEN = 1, SUBREG_FPODD = 2
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};
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}
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struct MipsRegisterInfo : public MipsGenRegisterInfo {
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const MipsSubtarget &Subtarget;
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const TargetInstrInfo &TII;
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@ -144,8 +144,10 @@ let Namespace = "Mips" in {
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// Subregister Set Definitions
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//===----------------------------------------------------------------------===//
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def mips_subreg_fpeven : PatLeaf<(i32 1)>;
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def mips_subreg_fpodd : PatLeaf<(i32 2)>;
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let Namespace = "Mips" in {
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def sub_fpeven : SubRegIndex { let NumberHack = 1; }
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def sub_fpodd : SubRegIndex { let NumberHack = 2; }
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}
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def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
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D8, D9, D10, D11, D12, D13, D14, D15],
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