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SubRegIndex'ize Mips 

llvm-svn: 104514
This commit is contained in:
Jakob Stoklund Olesen 2010-05-24 17:42:58 +00:00
parent fd6f16fab9
commit 5d56769fb6
3 changed files with 10 additions and 17 deletions
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12
llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
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@ -225,12 +225,12 @@ SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
MVT::Other, Offset0, Base, Chain); MVT::Other, Offset0, Base, Chain);
SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
dl, NVT), 0); dl, NVT), 0);
SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPEVEN, dl, SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
MVT::f64, Undef, SDValue(LD0, 0)); MVT::f64, Undef, SDValue(LD0, 0));
SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32, SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
MVT::Other, Offset1, Base, SDValue(LD0, 1)); MVT::Other, Offset1, Base, SDValue(LD0, 1));
SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl, SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
MVT::f64, I0, SDValue(LD1, 0)); MVT::f64, I0, SDValue(LD1, 0));
ReplaceUses(SDValue(N, 0), I1); ReplaceUses(SDValue(N, 0), I1);
@ -266,9 +266,9 @@ SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
// Get the even and odd part from the f64 register // Get the even and odd part from the f64 register
SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPODD, SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
dl, MVT::f32, N1); dl, MVT::f32, N1);
SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::SUBREG_FPEVEN, SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
dl, MVT::f32, N1); dl, MVT::f32, N1);
// The second store should start after for 4 bytes. // The second store should start after for 4 bytes.
@ -438,9 +438,9 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
SDValue Undef = SDValue( SDValue Undef = SDValue(
CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0); CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero); SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPEVEN, dl, SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
MVT::f64, Undef, SDValue(MTC, 0)); MVT::f64, Undef, SDValue(MTC, 0));
SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::SUBREG_FPODD, dl, SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
MVT::f64, I0, SDValue(MTC, 0)); MVT::f64, I0, SDValue(MTC, 0));
ReplaceUses(SDValue(Node, 0), I1); ReplaceUses(SDValue(Node, 0), I1);
return I1.getNode(); return I1.getNode();

9
llvm/lib/Target/Mips/MipsRegisterInfo.h
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@ -23,15 +23,6 @@ class MipsSubtarget;
class TargetInstrInfo; class TargetInstrInfo;
class Type; class Type;
namespace Mips {
/// SubregIndex - The index of various sized subregister classes. Note that
/// these indices must be kept in sync with the class indices in the
/// MipsRegisterInfo.td file.
enum SubregIndex {
SUBREG_FPEVEN = 1, SUBREG_FPODD = 2
};
}
struct MipsRegisterInfo : public MipsGenRegisterInfo { struct MipsRegisterInfo : public MipsGenRegisterInfo {
const MipsSubtarget &Subtarget; const MipsSubtarget &Subtarget;
const TargetInstrInfo &TII; const TargetInstrInfo &TII;

6
llvm/lib/Target/Mips/MipsRegisterInfo.td
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@ -144,8 +144,10 @@ let Namespace = "Mips" in {
// Subregister Set Definitions // Subregister Set Definitions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def mips_subreg_fpeven : PatLeaf<(i32 1)>; let Namespace = "Mips" in {
def mips_subreg_fpodd : PatLeaf<(i32 2)>; def sub_fpeven : SubRegIndex { let NumberHack = 1; }
def sub_fpodd : SubRegIndex { let NumberHack = 2; }
}
def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7, def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
D8, D9, D10, D11, D12, D13, D14, D15], D8, D9, D10, D11, D12, D13, D14, D15],