forked from OSchip/llvm-project
[WebAssembly] Bitselect intrinsic and instruction
Summary: Depends on D52755. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52805 llvm-svn: 343739
This commit is contained in:
Thomas Lively
parent
f7868ec25b
commit
5d461c96bd
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@ -91,6 +91,10 @@ def int_wasm_atomic_notify:
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// SIMD intrinsics
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//===----------------------------------------------------------------------===//
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def int_wasm_bitselect :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_anytrue :
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Intrinsic<[llvm_i32_ty],
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[llvm_anyvector_ty],
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@ -24,5 +24,6 @@ HANDLE_NODETYPE(BR_TABLE)
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HANDLE_NODETYPE(SHUFFLE)
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HANDLE_NODETYPE(ANYTRUE)
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HANDLE_NODETYPE(ALLTRUE)
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HANDLE_NODETYPE(BITSELECT)
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// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
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@ -965,6 +965,11 @@ WebAssemblyTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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switch (IntNo) {
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default:
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return {}; // Don't custom lower most intrinsics.
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case Intrinsic::wasm_bitselect:
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return DAG.getNode(WebAssemblyISD::BITSELECT, DL, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
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case Intrinsic::wasm_anytrue:
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case Intrinsic::wasm_alltrue: {
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unsigned OpCode = IntNo == Intrinsic::wasm_anytrue
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@ -972,6 +977,7 @@ WebAssemblyTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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: WebAssemblyISD::ALLTRUE;
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return DAG.getNode(OpCode, DL, Op.getValueType(), Op.getOperand(1));
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}
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case Intrinsic::wasm_lsda:
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// TODO For now, just return 0 not to crash
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return DAG.getConstant(0, DL, Op.getValueType());
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@ -20,8 +20,12 @@ def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
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// Custom nodes for custom operations
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def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
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def wasm_bitselect_t : SDTypeProfile<1, 3,
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[SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]
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>;
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def wasm_reduce_t : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>;
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def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
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def wasm_bitselect : SDNode<"WebAssemblyISD::BITSELECT", wasm_bitselect_t>;
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def wasm_anytrue : SDNode<"WebAssemblyISD::ANYTRUE", wasm_reduce_t>;
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def wasm_alltrue : SDNode<"WebAssemblyISD::ALLTRUE", wasm_reduce_t>;
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@ -193,6 +197,16 @@ multiclass SIMDNot<ValueType vec_t, PatFrag splat_pat, ValueType lane_t> {
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)],
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"v128.not\t$dst, $vec", "v128.not", 63>;
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}
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multiclass Bitselect<ValueType vec_t> {
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defm BITSELECT_#vec_t :
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SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
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[(set (vec_t V128:$dst),
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(vec_t (wasm_bitselect
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(vec_t V128:$c), (vec_t V128:$v1), (vec_t V128:$v2)
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))
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)],
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"v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 64>;
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}
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multiclass SIMDReduceVec<ValueType vec_t, string vec, string name, SDNode op,
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bits<32> simdop> {
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defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
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@ -380,6 +394,9 @@ defm "" : SIMDNot<v8i16, splat8, i32>;
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defm "" : SIMDNot<v4i32, splat4, i32>;
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defm "" : SIMDNot<v2i64, splat2, i64>;
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foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
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defm "" : Bitselect<vec_t>;
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defm ANYTRUE : SIMDReduce<"any_true", wasm_anytrue, 65>;
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defm ALLTRUE : SIMDReduce<"all_true", wasm_alltrue, 69>;
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@ -443,6 +460,13 @@ def : StorePatExternSymOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
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}
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// Bitselect is equivalent to (c & v1) | (~c & v2)
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foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
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def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)),
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(and (vnot V128:$c), (vec_t V128:$v2)))),
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(!cast<Instruction>("BITSELECT_"#vec_t)
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V128:$v1, V128:$v2, V128:$c)>;
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// Lower float comparisons that don't care about NaN to standard
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// WebAssembly float comparisons. These instructions are generated in
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// the target-independent expansion of unordered comparisons and
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@ -1,9 +1,9 @@
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM,SIMD128-VM-SLOW
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM,SIMD128-VM-FAST
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128,NO-SIMD128-SLOW
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128,NO-SIMD128-FAST
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; Test that basic SIMD128 arithmetic operations assemble as expected.
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@ -165,6 +165,27 @@ define <16 x i8> @not_v16i8(<16 x i8> %x) {
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ret <16 x i8> %a
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}
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; CHECK-LABEL: bitselect_v16i8:
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; NO-SIMD128-NOT: v128
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; SIMD128-NEXT: .param v128, v128, v128{{$}}
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; SIMD128-NEXT: .result v128{{$}}
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; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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; SIMD128-FAST-NEXT: v128.and
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; SIMD128-FAST-NEXT: v128.not
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; SIMD128-FAST-NEXT: v128.and
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; SIMD128-FAST-NEXT: v128.or
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; SIMD128-FAST-NEXT: return
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define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) {
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%masked_v1 = and <16 x i8> %c, %v1
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%inv_mask = xor <16 x i8> %c,
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<i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%masked_v2 = and <16 x i8> %inv_mask, %v2
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%a = or <16 x i8> %masked_v1, %masked_v2
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ret <16 x i8> %a
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}
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; ==============================================================================
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; 8 x i16
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; ==============================================================================
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@ -313,6 +334,27 @@ define <8 x i16> @not_v8i16(<8 x i16> %x) {
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ret <8 x i16> %a
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}
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; CHECK-LABEL: bitselect_v8i16:
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; NO-SIMD128-NOT: v128
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; SIMD128-NEXT: .param v128, v128, v128{{$}}
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; SIMD128-NEXT: .result v128{{$}}
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; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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; SIMD128-FAST-NEXT: v128.and
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; SIMD128-FAST-NEXT: v128.not
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; SIMD128-FAST-NEXT: v128.and
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; SIMD128-FAST-NEXT: v128.or
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; SIMD128-FAST-NEXT: return
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define <8 x i16> @bitselect_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) {
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%masked_v1 = and <8 x i16> %v1, %c
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%inv_mask = xor <8 x i16>
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<i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>,
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%c
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%masked_v2 = and <8 x i16> %v2, %inv_mask
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%a = or <8 x i16> %masked_v1, %masked_v2
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ret <8 x i16> %a
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}
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; ==============================================================================
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; 4 x i32
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; ==============================================================================
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@ -458,6 +500,25 @@ define <4 x i32> @not_v4i32(<4 x i32> %x) {
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ret <4 x i32> %a
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}
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; CHECK-LABEL: bitselect_v4i32:
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; NO-SIMD128-NOT: v128
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; SIMD128-NEXT: .param v128, v128, v128{{$}}
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; SIMD128-NEXT: .result v128{{$}}
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; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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; SIMD128-FAST-NEXT: v128.not
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; SIMD128-FAST-NEXT: v128.and
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; SIMD128-FAST-NEXT: v128.and
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; SIMD128-FAST-NEXT: v128.or
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; SIMD128-FAST-NEXT: return
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define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) {
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%masked_v1 = and <4 x i32> %c, %v1
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%inv_mask = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %c
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%masked_v2 = and <4 x i32> %inv_mask, %v2
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%a = or <4 x i32> %masked_v2, %masked_v1
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ret <4 x i32> %a
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}
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; ==============================================================================
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; 2 x i64
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; ==============================================================================
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@ -653,6 +714,26 @@ define <2 x i64> @not_v2i64(<2 x i64> %x) {
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ret <2 x i64> %a
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}
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; CHECK-LABEL: bitselect_v2i64:
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; NO-SIMD128-NOT: v128
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; SIMD128-VM-NOT: v128
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; SIMD128-NEXT: .param v128, v128, v128{{$}}
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; SIMD128-NEXT: .result v128{{$}}
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; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
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; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
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; SIMD128-FAST-NEXT: v128.not
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; SIMD128-FAST-NEXT: v128.and
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; SIMD128-FAST-NEXT: v128.and
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; SIMD128-FAST-NEXT: v128.or
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; SIMD128-FAST-NEXT: return
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define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) {
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%masked_v1 = and <2 x i64> %v1, %c
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%inv_mask = xor <2 x i64> <i64 -1, i64 -1>, %c
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%masked_v2 = and <2 x i64> %v2, %inv_mask
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%a = or <2 x i64> %masked_v2, %masked_v1
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ret <2 x i64> %a
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}
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; ==============================================================================
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; 4 x float
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; ==============================================================================
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@ -761,7 +842,6 @@ define <2 x double> @abs_v2f64(<2 x double> %x) {
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ret <2 x double> %a
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}
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; CHECK-LABEL: add_v2f64:
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; NO-SIMD128-NOT: f64x2
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; SIMD128-VM-NOT: f62x2
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@ -33,6 +33,19 @@ define i32 @all_v16i8(<16 x i8> %x) {
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ret i32 %a
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}
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; CHECK-LABEL: bitselect_v16i8:
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; SIMD128-NEXT: .param v128, v128, v128{{$}}
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; SIMD128-NEXT: .result v128{{$}}
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; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
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define <16 x i8> @bitselect_v16i8(<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2) {
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%a = call <16 x i8> @llvm.wasm.bitselect.v16i8(
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<16 x i8> %c, <16 x i8> %v1, <16 x i8> %v2
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)
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ret <16 x i8> %a
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}
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; ==============================================================================
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; 8 x i16
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; ==============================================================================
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@ -58,6 +71,19 @@ define i32 @all_v8i16(<8 x i16> %x) {
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ret i32 %a
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}
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; CHECK-LABEL: bitselect_v8i16:
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; SIMD128-NEXT: .param v128, v128, v128{{$}}
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; SIMD128-NEXT: .result v128{{$}}
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; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
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define <8 x i16> @bitselect_v8i16(<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2) {
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%a = call <8 x i16> @llvm.wasm.bitselect.v8i16(
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<8 x i16> %c, <8 x i16> %v1, <8 x i16> %v2
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)
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ret <8 x i16> %a
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}
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; ==============================================================================
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; 4 x i32
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; ==============================================================================
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@ -83,6 +109,19 @@ define i32 @all_v4i32(<4 x i32> %x) {
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ret i32 %a
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}
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; CHECK-LABEL: bitselect_v4i32:
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; SIMD128-NEXT: .param v128, v128, v128{{$}}
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; SIMD128-NEXT: .result v128{{$}}
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; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) {
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%a = call <4 x i32> @llvm.wasm.bitselect.v4i32(
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<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2
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)
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ret <4 x i32> %a
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}
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; ==============================================================================
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; 2 x i64
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; ==============================================================================
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@ -107,3 +146,48 @@ define i32 @all_v2i64(<2 x i64> %x) {
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%a = call i32 @llvm.wasm.alltrue.v2i64(<2 x i64> %x)
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ret i32 %a
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}
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; CHECK-LABEL: bitselect_v2i64:
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; SIMD128-NEXT: .param v128, v128, v128{{$}}
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; SIMD128-NEXT: .result v128{{$}}
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; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
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define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) {
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%a = call <2 x i64> @llvm.wasm.bitselect.v2i64(
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<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2
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)
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ret <2 x i64> %a
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}
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; ==============================================================================
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||||
; 4 x f32
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: bitselect_v4f32:
|
||||
; SIMD128-NEXT: .param v128, v128, v128{{$}}
|
||||
; SIMD128-NEXT: .result v128{{$}}
|
||||
; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
|
||||
; SIMD128-NEXT: return $pop[[R]]{{$}}
|
||||
declare <4 x float> @llvm.wasm.bitselect.v4f32(<4 x float>, <4 x float>, <4 x float>)
|
||||
define <4 x float> @bitselect_v4f32(<4 x float> %c, <4 x float> %v1, <4 x float> %v2) {
|
||||
%a = call <4 x float> @llvm.wasm.bitselect.v4f32(
|
||||
<4 x float> %c, <4 x float> %v1, <4 x float> %v2
|
||||
)
|
||||
ret <4 x float> %a
|
||||
}
|
||||
|
||||
; ==============================================================================
|
||||
; 2 x f64
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: bitselect_v2f64:
|
||||
; SIMD128-NEXT: .param v128, v128, v128{{$}}
|
||||
; SIMD128-NEXT: .result v128{{$}}
|
||||
; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
|
||||
; SIMD128-NEXT: return $pop[[R]]{{$}}
|
||||
declare <2 x double> @llvm.wasm.bitselect.v2f64(<2 x double>, <2 x double>, <2 x double>)
|
||||
define <2 x double> @bitselect_v2f64(<2 x double> %c, <2 x double> %v1, <2 x double> %v2) {
|
||||
%a = call <2 x double> @llvm.wasm.bitselect.v2f64(
|
||||
<2 x double> %c, <2 x double> %v1, <2 x double> %v2
|
||||
)
|
||||
ret <2 x double> %a
|
||||
}
|
||||
|
|
|
|||
|
|
@ -193,6 +193,9 @@
|
|||
# CHECK: v128.not # encoding: [0xfd,0x3f]
|
||||
v128.not
|
||||
|
||||
# CHECK: v128.bitselect # encoding: [0xfd,0x40]
|
||||
v128.bitselect
|
||||
|
||||
# CHECK: i8x16.any_true # encoding: [0xfd,0x41]
|
||||
i8x16.any_true
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue