forked from OSchip/llvm-project
RegisterPressure: Make liveness tracking subregister aware
Differential Revision: http://reviews.llvm.org/D14968 llvm-svn: 258258
This commit is contained in:
Matthias Braun
parent
3907fded1b
commit
5d458617aa
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@ -462,7 +462,7 @@ protected:
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void initRegPressure();
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void updatePressureDiffs(ArrayRef<unsigned> LiveUses);
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void updatePressureDiffs(ArrayRef<RegisterMaskPair> LiveUses);
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void updateScheduledPressure(const SUnit *SU,
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const std::vector<unsigned> &NewMaxPressure);
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@ -26,14 +26,22 @@ class LiveRange;
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class RegisterClassInfo;
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class MachineInstr;
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struct RegisterMaskPair {
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unsigned RegUnit; ///< Virtual register or register unit.
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LaneBitmask LaneMask;
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RegisterMaskPair(unsigned RegUnit, LaneBitmask LaneMask)
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: RegUnit(RegUnit), LaneMask(LaneMask) {}
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};
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/// Base class for register pressure results.
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struct RegisterPressure {
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/// Map of max reg pressure indexed by pressure set ID, not class ID.
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std::vector<unsigned> MaxSetPressure;
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/// List of live in virtual registers or physical register units.
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SmallVector<unsigned,8> LiveInRegs;
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SmallVector<unsigned,8> LiveOutRegs;
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SmallVector<RegisterMaskPair,8> LiveInRegs;
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SmallVector<RegisterMaskPair,8> LiveOutRegs;
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void dump(const TargetRegisterInfo *TRI) const;
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};
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@ -144,23 +152,30 @@ public:
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/// List of registers defined and used by a machine instruction.
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class RegisterOperands {
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public:
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/// List of virtual regiserts and register units read by the instruction.
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SmallVector<unsigned, 8> Uses;
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/// List of virtual registers and register units read by the instruction.
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SmallVector<RegisterMaskPair, 8> Uses;
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/// \brief List of virtual registers and register units defined by the
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/// instruction which are not dead.
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SmallVector<unsigned, 8> Defs;
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SmallVector<RegisterMaskPair, 8> Defs;
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/// \brief List of virtual registers and register units defined by the
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/// instruction but dead.
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SmallVector<unsigned, 8> DeadDefs;
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SmallVector<RegisterMaskPair, 8> DeadDefs;
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/// Analyze the given instruction \p MI and fill in the Uses, Defs and
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/// DeadDefs list based on the MachineOperand flags.
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void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI,
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const MachineRegisterInfo &MRI, bool IgnoreDead = false);
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const MachineRegisterInfo &MRI, bool TrackLaneMasks,
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bool IgnoreDead);
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/// Use liveness information to find dead defs not marked with a dead flag
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/// and move them to the DeadDefs vector.
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void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS);
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/// Use liveness information to find out which uses/defs are partially
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/// undefined/dead and adjust the RegisterMaskPairs accordingly.
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void adjustLaneLiveness(const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI, SlotIndex Pos);
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};
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/// Array of PressureDiffs.
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@ -225,7 +240,20 @@ struct RegPressureDelta {
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/// and virtual register indexes to an index usable by the sparse set.
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class LiveRegSet {
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private:
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SparseSet<unsigned> Regs;
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struct IndexMaskPair {
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unsigned Index;
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LaneBitmask LaneMask;
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IndexMaskPair(unsigned Index, LaneBitmask LaneMask)
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: Index(Index), LaneMask(LaneMask) {}
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unsigned getSparseSetIndex() const {
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return Index;
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}
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};
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typedef SparseSet<IndexMaskPair> RegSet;
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RegSet Regs;
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unsigned NumRegUnits;
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unsigned getSparseIndexFromReg(unsigned Reg) const {
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@ -244,19 +272,37 @@ public:
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void clear();
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void init(const MachineRegisterInfo &MRI);
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bool contains(unsigned Reg) const {
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LaneBitmask contains(unsigned Reg) const {
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unsigned SparseIndex = getSparseIndexFromReg(Reg);
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return Regs.count(SparseIndex);
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RegSet::const_iterator I = Regs.find(SparseIndex);
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if (I == Regs.end())
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return 0;
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return I->LaneMask;
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}
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bool insert(unsigned Reg) {
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unsigned SparseIndex = getSparseIndexFromReg(Reg);
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return Regs.insert(SparseIndex).second;
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/// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live.
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/// Returns the previously live lanes of \p Pair.Reg.
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LaneBitmask insert(RegisterMaskPair Pair) {
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unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
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auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask));
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if (!InsertRes.second) {
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unsigned PrevMask = InsertRes.first->LaneMask;
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InsertRes.first->LaneMask |= Pair.LaneMask;
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return PrevMask;
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}
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return 0;
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}
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bool erase(unsigned Reg) {
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unsigned SparseIndex = getSparseIndexFromReg(Reg);
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return Regs.erase(SparseIndex);
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/// Clears the \p Pair.LaneMask lanes of \p Pair.Reg (mark them as dead).
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/// Returns the previously live lanes of \p Pair.Reg.
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LaneBitmask erase(RegisterMaskPair Pair) {
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unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
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RegSet::iterator I = Regs.find(SparseIndex);
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if (I == Regs.end())
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return 0;
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unsigned PrevMask = I->LaneMask;
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I->LaneMask &= ~Pair.LaneMask;
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return PrevMask;
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}
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size_t size() const {
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@ -265,9 +311,10 @@ public:
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template<typename ContainerT>
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void appendTo(ContainerT &To) const {
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for (unsigned I : Regs) {
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unsigned Reg = getRegFromSparseIndex(I);
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To.push_back(Reg);
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for (const IndexMaskPair &P : Regs) {
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unsigned Reg = getRegFromSparseIndex(P.Index);
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if (P.LaneMask != 0)
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To.push_back(RegisterMaskPair(Reg, P.LaneMask));
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}
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}
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};
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@ -308,6 +355,9 @@ class RegPressureTracker {
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/// True if UntiedDefs will be populated.
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bool TrackUntiedDefs;
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/// True if lanemasks should be tracked.
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bool TrackLaneMasks;
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/// Register pressure corresponds to liveness before this instruction
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/// iterator. It may point to the end of the block or a DebugValue rather than
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/// an instruction.
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@ -327,23 +377,23 @@ class RegPressureTracker {
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public:
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RegPressureTracker(IntervalPressure &rp) :
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MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
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RequireIntervals(true), TrackUntiedDefs(false) {}
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RequireIntervals(true), TrackUntiedDefs(false), TrackLaneMasks(false) {}
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RegPressureTracker(RegionPressure &rp) :
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MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
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RequireIntervals(false), TrackUntiedDefs(false) {}
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RequireIntervals(false), TrackUntiedDefs(false), TrackLaneMasks(false) {}
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void reset();
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void init(const MachineFunction *mf, const RegisterClassInfo *rci,
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const LiveIntervals *lis, const MachineBasicBlock *mbb,
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MachineBasicBlock::const_iterator pos,
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bool ShouldTrackUntiedDefs = false);
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bool TrackLaneMasks, bool TrackUntiedDefs);
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/// Force liveness of virtual registers or physical register
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/// units. Particularly useful to initialize the livein/out state of the
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/// tracker before the first call to advance/recede.
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void addLiveRegs(ArrayRef<unsigned> Regs);
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void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
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/// Get the MI position corresponding to this register pressure.
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MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
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@ -355,14 +405,14 @@ public:
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void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }
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/// Recede across the previous instruction.
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void recede(SmallVectorImpl<unsigned> *LiveUses = nullptr);
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void recede(SmallVectorImpl<RegisterMaskPair> *LiveUses = nullptr);
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/// Recede across the previous instruction.
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/// This "low-level" variant assumes that recedeSkipDebugValues() was
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/// called previously and takes precomputed RegisterOperands for the
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/// instruction.
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void recede(const RegisterOperands &RegOpers,
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SmallVectorImpl<unsigned> *LiveUses = nullptr);
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SmallVectorImpl<RegisterMaskPair> *LiveUses = nullptr);
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/// Recede until we find an instruction which is not a DebugValue.
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void recedeSkipDebugValues();
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@ -469,18 +519,31 @@ public:
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void dump() const;
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protected:
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void discoverLiveOut(unsigned Reg);
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void discoverLiveIn(unsigned Reg);
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/// Add Reg to the live out set and increase max pressure.
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void discoverLiveOut(RegisterMaskPair Pair);
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/// Add Reg to the live in set and increase max pressure.
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void discoverLiveIn(RegisterMaskPair Pair);
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/// \brief Get the SlotIndex for the first nondebug instruction including or
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/// after the current position.
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SlotIndex getCurrSlot() const;
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void increaseRegPressure(ArrayRef<unsigned> Regs);
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void decreaseRegPressure(ArrayRef<unsigned> Regs);
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void increaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
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LaneBitmask NewMask);
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void decreaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
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LaneBitmask NewMask);
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void bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs);
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void bumpUpwardPressure(const MachineInstr *MI);
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void bumpDownwardPressure(const MachineInstr *MI);
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void discoverLiveInOrOut(RegisterMaskPair Pair,
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SmallVectorImpl<RegisterMaskPair> &LiveInOrOut);
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LaneBitmask getLastUsedLanes(unsigned RegUnit, SlotIndex Pos) const;
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LaneBitmask getLiveLanesAt(unsigned RegUnit, SlotIndex Pos) const;
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LaneBitmask getLiveThroughAt(unsigned RegUnit, SlotIndex Pos) const;
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};
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void dumpRegSetPressure(ArrayRef<unsigned> SetPressure,
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@ -874,8 +874,8 @@ void ScheduleDAGMILive::enterRegion(MachineBasicBlock *bb,
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// Setup the register pressure trackers for the top scheduled top and bottom
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// scheduled regions.
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void ScheduleDAGMILive::initRegPressure() {
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TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
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BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
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TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false);
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BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, false, false);
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// Close the RPTracker to finalize live ins.
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RPTracker.closeRegion();
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@ -905,7 +905,7 @@ void ScheduleDAGMILive::initRegPressure() {
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// Account for liveness generated by the region boundary.
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if (LiveRegionEnd != RegionEnd) {
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SmallVector<unsigned, 8> LiveUses;
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SmallVector<RegisterMaskPair, 8> LiveUses;
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BotRPTracker.recede(&LiveUses);
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updatePressureDiffs(LiveUses);
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}
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@ -969,10 +969,12 @@ updateScheduledPressure(const SUnit *SU,
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/// Update the PressureDiff array for liveness after scheduling this
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/// instruction.
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void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<unsigned> LiveUses) {
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for (unsigned LUIdx = 0, LUEnd = LiveUses.size(); LUIdx != LUEnd; ++LUIdx) {
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void ScheduleDAGMILive::updatePressureDiffs(
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ArrayRef<RegisterMaskPair> LiveUses) {
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for (const RegisterMaskPair &P : LiveUses) {
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/// FIXME: Currently assuming single-use physregs.
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unsigned Reg = LiveUses[LUIdx];
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unsigned Reg = P.RegUnit;
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assert(P.LaneMask != 0);
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DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
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if (!TRI->isVirtualRegister(Reg))
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continue;
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@ -1111,7 +1113,7 @@ void ScheduleDAGMILive::buildDAGWithRegPressure() {
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// Initialize the register pressure tracker used by buildSchedGraph.
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RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
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/*TrackUntiedDefs=*/true);
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false, /*TrackUntiedDefs=*/true);
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// Account for liveness generate by the region boundary.
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if (LiveRegionEnd != RegionEnd)
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@ -1167,10 +1169,8 @@ unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
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unsigned MaxCyclicLatency = 0;
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// Visit each live out vreg def to find def/use pairs that cross iterations.
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ArrayRef<unsigned> LiveOuts = RPTracker.getPressure().LiveOutRegs;
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for (ArrayRef<unsigned>::iterator RI = LiveOuts.begin(), RE = LiveOuts.end();
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RI != RE; ++RI) {
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unsigned Reg = *RI;
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for (const RegisterMaskPair &P : RPTracker.getPressure().LiveOutRegs) {
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unsigned Reg = P.RegUnit;
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if (!TRI->isVirtualRegister(Reg))
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continue;
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const LiveInterval &LI = LIS->getInterval(Reg);
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@ -1265,7 +1265,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
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}
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if (ShouldTrackPressure) {
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// Update bottom scheduled pressure.
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SmallVector<unsigned, 8> LiveUses;
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SmallVector<RegisterMaskPair, 8> LiveUses;
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BotRPTracker.recede(&LiveUses);
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assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
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DEBUG(
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@ -24,7 +24,13 @@ using namespace llvm;
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/// Increase pressure for each pressure set provided by TargetRegisterInfo.
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static void increaseSetPressure(std::vector<unsigned> &CurrSetPressure,
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PSetIterator PSetI) {
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const MachineRegisterInfo &MRI, unsigned Reg,
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LaneBitmask PrevMask, LaneBitmask NewMask) {
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assert((PrevMask & ~NewMask) == 0 && "Must not remove bits");
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if (PrevMask != 0 || NewMask == 0)
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return;
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PSetIterator PSetI = MRI.getPressureSets(Reg);
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unsigned Weight = PSetI.getWeight();
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for (; PSetI.isValid(); ++PSetI)
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CurrSetPressure[*PSetI] += Weight;
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@ -32,7 +38,13 @@ static void increaseSetPressure(std::vector<unsigned> &CurrSetPressure,
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/// Decrease pressure for each pressure set provided by TargetRegisterInfo.
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static void decreaseSetPressure(std::vector<unsigned> &CurrSetPressure,
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PSetIterator PSetI) {
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const MachineRegisterInfo &MRI, unsigned Reg,
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LaneBitmask PrevMask, LaneBitmask NewMask) {
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assert((NewMask & !PrevMask) == 0 && "Must not add bits");
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if (NewMask != 0 || PrevMask == 0)
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return;
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PSetIterator PSetI = MRI.getPressureSets(Reg);
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unsigned Weight = PSetI.getWeight();
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for (; PSetI.isValid(); ++PSetI) {
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assert(CurrSetPressure[*PSetI] >= Weight && "register pressure underflow");
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@ -59,12 +71,20 @@ void RegisterPressure::dump(const TargetRegisterInfo *TRI) const {
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dbgs() << "Max Pressure: ";
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dumpRegSetPressure(MaxSetPressure, TRI);
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dbgs() << "Live In: ";
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for (unsigned Reg : LiveInRegs)
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dbgs() << PrintVRegOrUnit(Reg, TRI) << " ";
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for (const RegisterMaskPair &P : LiveInRegs) {
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dbgs() << PrintVRegOrUnit(P.RegUnit, TRI);
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if (P.LaneMask != ~0u)
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dbgs() << ':' << PrintLaneMask(P.LaneMask);
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dbgs() << ' ';
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}
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dbgs() << '\n';
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dbgs() << "Live Out: ";
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for (unsigned Reg : LiveOutRegs)
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dbgs() << PrintVRegOrUnit(Reg, TRI) << " ";
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for (const RegisterMaskPair &P : LiveOutRegs) {
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dbgs() << PrintVRegOrUnit(P.RegUnit, TRI);
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if (P.LaneMask != ~0u)
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dbgs() << ':' << PrintLaneMask(P.LaneMask);
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dbgs() << ' ';
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}
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dbgs() << '\n';
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}
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@ -89,24 +109,25 @@ void PressureDiff::dump(const TargetRegisterInfo &TRI) const {
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dbgs() << '\n';
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}
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/// Increase the current pressure as impacted by these registers and bump
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/// the high water mark if needed.
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void RegPressureTracker::increaseRegPressure(ArrayRef<unsigned> RegUnits) {
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for (unsigned RegUnit : RegUnits) {
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PSetIterator PSetI = MRI->getPressureSets(RegUnit);
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unsigned Weight = PSetI.getWeight();
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for (; PSetI.isValid(); ++PSetI) {
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CurrSetPressure[*PSetI] += Weight;
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P.MaxSetPressure[*PSetI] =
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std::max(P.MaxSetPressure[*PSetI], CurrSetPressure[*PSetI]);
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}
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void RegPressureTracker::increaseRegPressure(unsigned RegUnit,
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LaneBitmask PreviousMask,
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LaneBitmask NewMask) {
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if (PreviousMask != 0 || NewMask == 0)
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return;
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PSetIterator PSetI = MRI->getPressureSets(RegUnit);
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unsigned Weight = PSetI.getWeight();
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for (; PSetI.isValid(); ++PSetI) {
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CurrSetPressure[*PSetI] += Weight;
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P.MaxSetPressure[*PSetI] =
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std::max(P.MaxSetPressure[*PSetI], CurrSetPressure[*PSetI]);
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}
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}
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/// Simply decrease the current pressure as impacted by these registers.
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void RegPressureTracker::decreaseRegPressure(ArrayRef<unsigned> RegUnits) {
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for (unsigned RegUnit : RegUnits)
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decreaseSetPressure(CurrSetPressure, MRI->getPressureSets(RegUnit));
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void RegPressureTracker::decreaseRegPressure(unsigned RegUnit,
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LaneBitmask PreviousMask,
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LaneBitmask NewMask) {
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decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask);
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}
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/// Clear the result so it can be used for another round of pressure tracking.
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@ -201,8 +222,7 @@ void RegPressureTracker::init(const MachineFunction *mf,
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const LiveIntervals *lis,
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const MachineBasicBlock *mbb,
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MachineBasicBlock::const_iterator pos,
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bool ShouldTrackUntiedDefs)
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{
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bool TrackLaneMasks, bool TrackUntiedDefs) {
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reset();
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MF = mf;
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|
|
@ -210,7 +230,8 @@ void RegPressureTracker::init(const MachineFunction *mf,
|
|||
RCI = rci;
|
||||
MRI = &MF->getRegInfo();
|
||||
MBB = mbb;
|
||||
TrackUntiedDefs = ShouldTrackUntiedDefs;
|
||||
this->TrackUntiedDefs = TrackUntiedDefs;
|
||||
this->TrackLaneMasks = TrackLaneMasks;
|
||||
|
||||
if (RequireIntervals) {
|
||||
assert(lis && "IntervalPressure requires LiveIntervals");
|
||||
|
|
@ -297,20 +318,92 @@ void RegPressureTracker::closeRegion() {
|
|||
void RegPressureTracker::initLiveThru(const RegPressureTracker &RPTracker) {
|
||||
LiveThruPressure.assign(TRI->getNumRegPressureSets(), 0);
|
||||
assert(isBottomClosed() && "need bottom-up tracking to intialize.");
|
||||
for (unsigned Reg : P.LiveOutRegs) {
|
||||
if (TargetRegisterInfo::isVirtualRegister(Reg)
|
||||
&& !RPTracker.hasUntiedDef(Reg)) {
|
||||
increaseSetPressure(LiveThruPressure, MRI->getPressureSets(Reg));
|
||||
}
|
||||
for (const RegisterMaskPair &Pair : P.LiveOutRegs) {
|
||||
unsigned RegUnit = Pair.RegUnit;
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegUnit)
|
||||
&& !RPTracker.hasUntiedDef(RegUnit))
|
||||
increaseSetPressure(LiveThruPressure, *MRI, RegUnit, 0, Pair.LaneMask);
|
||||
}
|
||||
}
|
||||
|
||||
/// \brief Convenient wrapper for checking membership in RegisterOperands.
|
||||
/// (std::count() doesn't have an early exit).
|
||||
static bool containsReg(ArrayRef<unsigned> RegUnits, unsigned RegUnit) {
|
||||
return std::find(RegUnits.begin(), RegUnits.end(), RegUnit) != RegUnits.end();
|
||||
static unsigned getRegLanes(ArrayRef<RegisterMaskPair> RegUnits,
|
||||
unsigned RegUnit) {
|
||||
auto I = std::find_if(RegUnits.begin(), RegUnits.end(),
|
||||
[RegUnit](const RegisterMaskPair Other) {
|
||||
return Other.RegUnit == RegUnit;
|
||||
});
|
||||
if (I == RegUnits.end())
|
||||
return 0;
|
||||
return I->LaneMask;
|
||||
}
|
||||
|
||||
static void addRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
|
||||
RegisterMaskPair Pair) {
|
||||
unsigned RegUnit = Pair.RegUnit;
|
||||
assert(Pair.LaneMask != 0);
|
||||
auto I = std::find_if(RegUnits.begin(), RegUnits.end(),
|
||||
[RegUnit](const RegisterMaskPair Other) {
|
||||
return Other.RegUnit == RegUnit;
|
||||
});
|
||||
if (I == RegUnits.end()) {
|
||||
RegUnits.push_back(Pair);
|
||||
} else {
|
||||
I->LaneMask |= Pair.LaneMask;
|
||||
}
|
||||
}
|
||||
|
||||
static void removeRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
|
||||
RegisterMaskPair Pair) {
|
||||
unsigned RegUnit = Pair.RegUnit;
|
||||
assert(Pair.LaneMask != 0);
|
||||
auto I = std::find_if(RegUnits.begin(), RegUnits.end(),
|
||||
[RegUnit](const RegisterMaskPair Other) {
|
||||
return Other.RegUnit == RegUnit;
|
||||
});
|
||||
if (I != RegUnits.end()) {
|
||||
I->LaneMask &= ~Pair.LaneMask;
|
||||
if (I->LaneMask == 0)
|
||||
RegUnits.erase(I);
|
||||
}
|
||||
}
|
||||
|
||||
static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS,
|
||||
const MachineRegisterInfo &MRI, bool TrackLaneMasks, unsigned RegUnit,
|
||||
SlotIndex Pos,
|
||||
bool(*Property)(const LiveRange &LR, SlotIndex Pos)) {
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
|
||||
const LiveInterval &LI = LIS.getInterval(RegUnit);
|
||||
LaneBitmask Result = 0;
|
||||
if (TrackLaneMasks && LI.hasSubRanges()) {
|
||||
for (const LiveInterval::SubRange &SR : LI.subranges()) {
|
||||
if (Property(SR, Pos))
|
||||
Result |= SR.LaneMask;
|
||||
}
|
||||
} else if (Property(LI, Pos))
|
||||
Result = MRI.getMaxLaneMaskForVReg(RegUnit);
|
||||
|
||||
return Result;
|
||||
} else {
|
||||
const LiveRange *LR = LIS.getCachedRegUnit(RegUnit);
|
||||
// Be prepared for missing liveranges: We usually do not compute liveranges
|
||||
// for physical registers on targets with many registers (GPUs).
|
||||
if (LR == nullptr)
|
||||
return 0;
|
||||
return Property(*LR, Pos) ? ~0u : 0;
|
||||
}
|
||||
}
|
||||
|
||||
static LaneBitmask getLiveLanesAt(const LiveIntervals &LIS,
|
||||
const MachineRegisterInfo &MRI,
|
||||
bool TrackLaneMasks, unsigned RegUnit,
|
||||
SlotIndex Pos) {
|
||||
return getLanesWithProperty(LIS, MRI, TrackLaneMasks, RegUnit, Pos,
|
||||
[](const LiveRange &LR, SlotIndex Pos) {
|
||||
return LR.liveAt(Pos);
|
||||
});
|
||||
}
|
||||
|
||||
|
||||
namespace {
|
||||
|
||||
/// Collect this instruction's unique uses and defs into SmallVectors for
|
||||
|
|
@ -321,23 +414,23 @@ class RegisterOperandsCollector {
|
|||
RegisterOperands &RegOpers;
|
||||
const TargetRegisterInfo &TRI;
|
||||
const MachineRegisterInfo &MRI;
|
||||
bool TrackLaneMasks;
|
||||
bool IgnoreDead;
|
||||
|
||||
RegisterOperandsCollector(RegisterOperands &RegOpers,
|
||||
const TargetRegisterInfo &TRI,
|
||||
const MachineRegisterInfo &MRI,
|
||||
bool IgnoreDead)
|
||||
: RegOpers(RegOpers), TRI(TRI), MRI(MRI), IgnoreDead(IgnoreDead) {}
|
||||
bool TrackLaneMasks, bool IgnoreDead)
|
||||
: RegOpers(RegOpers), TRI(TRI), MRI(MRI),
|
||||
TrackLaneMasks(TrackLaneMasks), IgnoreDead(IgnoreDead) {}
|
||||
|
||||
void collectInstr(const MachineInstr &MI) const {
|
||||
for (ConstMIBundleOperands OperI(&MI); OperI.isValid(); ++OperI)
|
||||
collectOperand(*OperI);
|
||||
|
||||
// Remove redundant physreg dead defs.
|
||||
SmallVectorImpl<unsigned>::iterator I =
|
||||
std::remove_if(RegOpers.DeadDefs.begin(), RegOpers.DeadDefs.end(),
|
||||
std::bind1st(std::ptr_fun(containsReg), RegOpers.Defs));
|
||||
RegOpers.DeadDefs.erase(I, RegOpers.DeadDefs.end());
|
||||
for (const RegisterMaskPair &P : RegOpers.Defs)
|
||||
removeRegLanes(RegOpers.DeadDefs, P);
|
||||
}
|
||||
|
||||
/// Push this operand's register onto the correct vectors.
|
||||
|
|
@ -345,28 +438,39 @@ class RegisterOperandsCollector {
|
|||
if (!MO.isReg() || !MO.getReg())
|
||||
return;
|
||||
unsigned Reg = MO.getReg();
|
||||
if (MO.readsReg())
|
||||
pushRegUnits(Reg, RegOpers.Uses);
|
||||
if (MO.isDef()) {
|
||||
unsigned SubRegIdx = MO.getSubReg();
|
||||
if (MO.isUse()) {
|
||||
if (!MO.isUndef() && !MO.isInternalRead())
|
||||
pushRegUnits(Reg, SubRegIdx, RegOpers.Uses);
|
||||
} else {
|
||||
assert(MO.isDef());
|
||||
if (MO.isUndef()) {
|
||||
// Treat read-undef subreg defs as definitions of the whole register.
|
||||
SubRegIdx = 0;
|
||||
} else if (!TrackLaneMasks && SubRegIdx != 0 && !MO.isInternalRead()) {
|
||||
// Interpret the subregister def as read-modify-store: A use+def of the
|
||||
// full register.
|
||||
pushRegUnits(Reg, SubRegIdx, RegOpers.Uses);
|
||||
}
|
||||
|
||||
if (MO.isDead()) {
|
||||
if (!IgnoreDead)
|
||||
pushRegUnits(Reg, RegOpers.DeadDefs);
|
||||
pushRegUnits(Reg, SubRegIdx, RegOpers.DeadDefs);
|
||||
} else
|
||||
pushRegUnits(Reg, RegOpers.Defs);
|
||||
pushRegUnits(Reg, SubRegIdx, RegOpers.Defs);
|
||||
}
|
||||
}
|
||||
|
||||
void pushRegUnits(unsigned Reg, SmallVectorImpl<unsigned> &RegUnits) const {
|
||||
void pushRegUnits(unsigned Reg, unsigned SubRegIdx,
|
||||
SmallVectorImpl<RegisterMaskPair> &RegUnits) const {
|
||||
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
||||
if (containsReg(RegUnits, Reg))
|
||||
return;
|
||||
RegUnits.push_back(Reg);
|
||||
LaneBitmask LaneMask = TrackLaneMasks && SubRegIdx != 0
|
||||
? TRI.getSubRegIndexLaneMask(SubRegIdx)
|
||||
: MRI.getMaxLaneMaskForVReg(Reg);
|
||||
addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneMask));
|
||||
} else if (MRI.isAllocatable(Reg)) {
|
||||
for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) {
|
||||
if (containsReg(RegUnits, *Units))
|
||||
continue;
|
||||
RegUnits.push_back(*Units);
|
||||
}
|
||||
for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
|
||||
addRegLanes(RegUnits, RegisterMaskPair(*Units, ~0u));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -378,24 +482,24 @@ class RegisterOperandsCollector {
|
|||
void RegisterOperands::collect(const MachineInstr &MI,
|
||||
const TargetRegisterInfo &TRI,
|
||||
const MachineRegisterInfo &MRI,
|
||||
bool IgnoreDead) {
|
||||
RegisterOperandsCollector Collector(*this, TRI, MRI, IgnoreDead);
|
||||
bool TrackLaneMasks, bool IgnoreDead) {
|
||||
RegisterOperandsCollector Collector(*this, TRI, MRI, TrackLaneMasks,
|
||||
IgnoreDead);
|
||||
Collector.collectInstr(MI);
|
||||
}
|
||||
|
||||
void RegisterOperands::detectDeadDefs(const MachineInstr &MI,
|
||||
const LiveIntervals &LIS) {
|
||||
SlotIndex SlotIdx = LIS.getInstructionIndex(&MI);
|
||||
for (SmallVectorImpl<unsigned>::iterator RI = Defs.begin();
|
||||
RI != Defs.end(); /*empty*/) {
|
||||
unsigned Reg = *RI;
|
||||
for (auto RI = Defs.begin(); RI != Defs.end(); /*empty*/) {
|
||||
unsigned Reg = RI->RegUnit;
|
||||
const LiveRange *LR = getLiveRange(LIS, Reg);
|
||||
if (LR != nullptr) {
|
||||
LiveQueryResult LRQ = LR->Query(SlotIdx);
|
||||
if (LRQ.isDeadDef()) {
|
||||
// LiveIntervals knows this is a dead even though it's MachineOperand is
|
||||
// not flagged as such.
|
||||
DeadDefs.push_back(Reg);
|
||||
DeadDefs.push_back(*RI);
|
||||
RI = Defs.erase(RI);
|
||||
continue;
|
||||
}
|
||||
|
|
@ -404,6 +508,38 @@ void RegisterOperands::detectDeadDefs(const MachineInstr &MI,
|
|||
}
|
||||
}
|
||||
|
||||
void RegisterOperands::adjustLaneLiveness(const LiveIntervals &LIS,
|
||||
const MachineRegisterInfo &MRI,
|
||||
SlotIndex Pos) {
|
||||
for (auto I = Defs.begin(); I != Defs.end(); ) {
|
||||
LaneBitmask LiveAfter = getLiveLanesAt(LIS, MRI, true, I->RegUnit,
|
||||
Pos.getDeadSlot());
|
||||
#if 0
|
||||
unsigned DeadDef = I->LaneMask & ~LiveAfter;
|
||||
if (DeadDef != 0)
|
||||
addRegLanes(DeadDefs, RegisterMaskPair(I->RegUnit, DeadDef));
|
||||
#endif
|
||||
unsigned LaneMask = I->LaneMask & LiveAfter;
|
||||
if (LaneMask == 0)
|
||||
I = Defs.erase(I);
|
||||
else {
|
||||
I->LaneMask = LaneMask;
|
||||
++I;
|
||||
}
|
||||
}
|
||||
for (auto I = Uses.begin(); I != Uses.end(); ) {
|
||||
LaneBitmask LiveBefore = getLiveLanesAt(LIS, MRI, true, I->RegUnit,
|
||||
Pos.getBaseIndex());
|
||||
unsigned LaneMask = I->LaneMask & LiveBefore;
|
||||
if (LaneMask == 0) {
|
||||
I = Uses.erase(I);
|
||||
} else {
|
||||
I->LaneMask = LaneMask;
|
||||
++I;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Initialize an array of N PressureDiffs.
|
||||
void PressureDiffs::init(unsigned N) {
|
||||
Size = N;
|
||||
|
|
@ -421,11 +557,11 @@ void PressureDiffs::addInstruction(unsigned Idx,
|
|||
const MachineRegisterInfo &MRI) {
|
||||
PressureDiff &PDiff = (*this)[Idx];
|
||||
assert(!PDiff.begin()->isValid() && "stale PDiff");
|
||||
for (unsigned Reg : RegOpers.Defs)
|
||||
PDiff.addPressureChange(Reg, true, &MRI);
|
||||
for (const RegisterMaskPair &P : RegOpers.Defs)
|
||||
PDiff.addPressureChange(P.RegUnit, true, &MRI);
|
||||
|
||||
for (unsigned Reg : RegOpers.Uses)
|
||||
PDiff.addPressureChange(Reg, false, &MRI);
|
||||
for (const RegisterMaskPair &P : RegOpers.Uses)
|
||||
PDiff.addPressureChange(P.RegUnit, false, &MRI);
|
||||
}
|
||||
|
||||
/// Add a change in pressure to the pressure diff of a given instruction.
|
||||
|
|
@ -465,33 +601,59 @@ void PressureDiff::addPressureChange(unsigned RegUnit, bool IsDec,
|
|||
}
|
||||
|
||||
/// Force liveness of registers.
|
||||
void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) {
|
||||
for (unsigned Reg : Regs) {
|
||||
if (LiveRegs.insert(Reg))
|
||||
increaseRegPressure(Reg);
|
||||
void RegPressureTracker::addLiveRegs(ArrayRef<RegisterMaskPair> Regs) {
|
||||
for (const RegisterMaskPair &P : Regs) {
|
||||
unsigned PrevMask = LiveRegs.insert(P);
|
||||
unsigned NewMask = PrevMask | P.LaneMask;
|
||||
increaseRegPressure(P.RegUnit, PrevMask, NewMask);
|
||||
}
|
||||
}
|
||||
|
||||
/// Add Reg to the live in set and increase max pressure.
|
||||
void RegPressureTracker::discoverLiveIn(unsigned Reg) {
|
||||
assert(!LiveRegs.contains(Reg) && "avoid bumping max pressure twice");
|
||||
if (containsReg(P.LiveInRegs, Reg))
|
||||
void RegPressureTracker::discoverLiveInOrOut(RegisterMaskPair Pair,
|
||||
SmallVectorImpl<RegisterMaskPair> &LiveInOrOut) {
|
||||
if (Pair.LaneMask == 0)
|
||||
return;
|
||||
|
||||
// At live in discovery, unconditionally increase the high water mark.
|
||||
P.LiveInRegs.push_back(Reg);
|
||||
increaseSetPressure(P.MaxSetPressure, MRI->getPressureSets(Reg));
|
||||
unsigned RegUnit = Pair.RegUnit;
|
||||
auto I = std::find_if(LiveInOrOut.begin(), LiveInOrOut.end(),
|
||||
[RegUnit](const RegisterMaskPair &Other) {
|
||||
return Other.RegUnit == RegUnit;
|
||||
});
|
||||
LaneBitmask PrevMask;
|
||||
LaneBitmask NewMask;
|
||||
if (I == LiveInOrOut.end()) {
|
||||
PrevMask = 0;
|
||||
NewMask = Pair.LaneMask;
|
||||
LiveInOrOut.push_back(Pair);
|
||||
} else {
|
||||
PrevMask = I->LaneMask;
|
||||
NewMask = PrevMask | Pair.LaneMask;
|
||||
I->LaneMask = NewMask;
|
||||
}
|
||||
increaseSetPressure(P.MaxSetPressure, *MRI, RegUnit, PrevMask, NewMask);
|
||||
}
|
||||
|
||||
/// Add Reg to the live out set and increase max pressure.
|
||||
void RegPressureTracker::discoverLiveOut(unsigned Reg) {
|
||||
assert(!LiveRegs.contains(Reg) && "avoid bumping max pressure twice");
|
||||
if (containsReg(P.LiveOutRegs, Reg))
|
||||
return;
|
||||
void RegPressureTracker::discoverLiveIn(RegisterMaskPair Pair) {
|
||||
discoverLiveInOrOut(Pair, P.LiveInRegs);
|
||||
}
|
||||
|
||||
// At live out discovery, unconditionally increase the high water mark.
|
||||
P.LiveOutRegs.push_back(Reg);
|
||||
increaseSetPressure(P.MaxSetPressure, MRI->getPressureSets(Reg));
|
||||
void RegPressureTracker::discoverLiveOut(RegisterMaskPair Pair) {
|
||||
discoverLiveInOrOut(Pair, P.LiveOutRegs);
|
||||
}
|
||||
|
||||
void RegPressureTracker::bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs) {
|
||||
for (const RegisterMaskPair &P : DeadDefs) {
|
||||
unsigned Reg = P.RegUnit;
|
||||
LaneBitmask LiveMask = LiveRegs.contains(Reg);
|
||||
LaneBitmask BumpedMask = LiveMask | P.LaneMask;
|
||||
increaseRegPressure(Reg, LiveMask, BumpedMask);
|
||||
}
|
||||
for (const RegisterMaskPair &P : DeadDefs) {
|
||||
unsigned Reg = P.RegUnit;
|
||||
LaneBitmask LiveMask = LiveRegs.contains(Reg);
|
||||
LaneBitmask BumpedMask = LiveMask | P.LaneMask;
|
||||
decreaseRegPressure(Reg, BumpedMask, LiveMask);
|
||||
}
|
||||
}
|
||||
|
||||
/// Recede across the previous instruction. If LiveUses is provided, record any
|
||||
|
|
@ -500,20 +662,29 @@ void RegPressureTracker::discoverLiveOut(unsigned Reg) {
|
|||
/// difference pointer is provided record the changes is pressure caused by this
|
||||
/// instruction independent of liveness.
|
||||
void RegPressureTracker::recede(const RegisterOperands &RegOpers,
|
||||
SmallVectorImpl<unsigned> *LiveUses) {
|
||||
SmallVectorImpl<RegisterMaskPair> *LiveUses) {
|
||||
assert(!CurrPos->isDebugValue());
|
||||
|
||||
// Boost pressure for all dead defs together.
|
||||
increaseRegPressure(RegOpers.DeadDefs);
|
||||
decreaseRegPressure(RegOpers.DeadDefs);
|
||||
bumpDeadDefs(RegOpers.DeadDefs);
|
||||
|
||||
// Kill liveness at live defs.
|
||||
// TODO: consider earlyclobbers?
|
||||
for (unsigned Reg : RegOpers.Defs) {
|
||||
if (LiveRegs.erase(Reg))
|
||||
decreaseRegPressure(Reg);
|
||||
else
|
||||
discoverLiveOut(Reg);
|
||||
for (const RegisterMaskPair &Def : RegOpers.Defs) {
|
||||
unsigned Reg = Def.RegUnit;
|
||||
|
||||
LaneBitmask PreviousMask = LiveRegs.erase(Def);
|
||||
LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;
|
||||
|
||||
LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
|
||||
if (LiveOut != 0) {
|
||||
discoverLiveOut(RegisterMaskPair(Reg, LiveOut));
|
||||
// Retroactively model effects on pressure of the live out lanes.
|
||||
increaseSetPressure(CurrSetPressure, *MRI, Reg, 0, LiveOut);
|
||||
PreviousMask = LiveOut;
|
||||
}
|
||||
|
||||
decreaseRegPressure(Reg, PreviousMask, NewMask);
|
||||
}
|
||||
|
||||
SlotIndex SlotIdx;
|
||||
|
|
@ -521,27 +692,34 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers,
|
|||
SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
|
||||
|
||||
// Generate liveness for uses.
|
||||
for (unsigned Reg : RegOpers.Uses) {
|
||||
if (!LiveRegs.contains(Reg)) {
|
||||
// Adjust liveouts if LiveIntervals are available.
|
||||
if (RequireIntervals) {
|
||||
const LiveRange *LR = getLiveRange(*LIS, Reg);
|
||||
if (LR) {
|
||||
LiveQueryResult LRQ = LR->Query(SlotIdx);
|
||||
if (!LRQ.isKill() && !LRQ.valueDefined())
|
||||
discoverLiveOut(Reg);
|
||||
}
|
||||
for (const RegisterMaskPair &Use : RegOpers.Uses) {
|
||||
unsigned Reg = Use.RegUnit;
|
||||
assert(Use.LaneMask != 0);
|
||||
LaneBitmask PreviousMask = LiveRegs.insert(Use);
|
||||
LaneBitmask NewMask = PreviousMask | Use.LaneMask;
|
||||
if (NewMask == PreviousMask)
|
||||
continue;
|
||||
|
||||
// Did the register just become live?
|
||||
if (PreviousMask == 0) {
|
||||
if (LiveUses != nullptr) {
|
||||
unsigned NewLanes = NewMask & ~PreviousMask;
|
||||
addRegLanes(*LiveUses, RegisterMaskPair(Reg, NewLanes));
|
||||
}
|
||||
increaseRegPressure(Reg);
|
||||
LiveRegs.insert(Reg);
|
||||
if (LiveUses && !containsReg(*LiveUses, Reg))
|
||||
LiveUses->push_back(Reg);
|
||||
|
||||
// Discover live outs if this may be the first occurance of this register.
|
||||
LaneBitmask LiveOut = getLiveThroughAt(Reg, SlotIdx);
|
||||
discoverLiveOut(RegisterMaskPair(Reg, LiveOut));
|
||||
}
|
||||
|
||||
increaseRegPressure(Reg, PreviousMask, NewMask);
|
||||
}
|
||||
if (TrackUntiedDefs) {
|
||||
for (unsigned Reg : RegOpers.Defs) {
|
||||
if (TargetRegisterInfo::isVirtualRegister(Reg) && !LiveRegs.contains(Reg))
|
||||
UntiedDefs.insert(Reg);
|
||||
for (const RegisterMaskPair &Def : RegOpers.Defs) {
|
||||
unsigned RegUnit = Def.RegUnit;
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegUnit) &&
|
||||
(LiveRegs.contains(RegUnit) & Def.LaneMask) == 0)
|
||||
UntiedDefs.insert(RegUnit);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -569,14 +747,18 @@ void RegPressureTracker::recedeSkipDebugValues() {
|
|||
static_cast<IntervalPressure&>(P).openTop(SlotIdx);
|
||||
}
|
||||
|
||||
void RegPressureTracker::recede(SmallVectorImpl<unsigned> *LiveUses) {
|
||||
void RegPressureTracker::recede(SmallVectorImpl<RegisterMaskPair> *LiveUses) {
|
||||
recedeSkipDebugValues();
|
||||
|
||||
const MachineInstr &MI = *CurrPos;
|
||||
RegisterOperands RegOpers;
|
||||
RegOpers.collect(MI, *TRI, *MRI);
|
||||
if (RequireIntervals)
|
||||
RegOpers.collect(MI, *TRI, *MRI, TrackLaneMasks, false);
|
||||
if (TrackLaneMasks) {
|
||||
SlotIndex SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
|
||||
RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
|
||||
} else if (RequireIntervals) {
|
||||
RegOpers.detectDeadDefs(MI, *LIS);
|
||||
}
|
||||
|
||||
recede(RegOpers, LiveUses);
|
||||
}
|
||||
|
|
@ -602,38 +784,36 @@ void RegPressureTracker::advance() {
|
|||
}
|
||||
|
||||
RegisterOperands RegOpers;
|
||||
RegOpers.collect(*CurrPos, *TRI, *MRI);
|
||||
RegOpers.collect(*CurrPos, *TRI, *MRI, TrackLaneMasks, false);
|
||||
if (TrackLaneMasks)
|
||||
RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
|
||||
|
||||
for (unsigned Reg : RegOpers.Uses) {
|
||||
// Discover live-ins.
|
||||
bool isLive = LiveRegs.contains(Reg);
|
||||
if (!isLive)
|
||||
discoverLiveIn(Reg);
|
||||
// Kill liveness at last uses.
|
||||
bool lastUse = false;
|
||||
if (RequireIntervals) {
|
||||
const LiveRange *LR = getLiveRange(*LIS, Reg);
|
||||
lastUse = LR && LR->Query(SlotIdx).isKill();
|
||||
} else {
|
||||
// Allocatable physregs are always single-use before register rewriting.
|
||||
lastUse = !TargetRegisterInfo::isVirtualRegister(Reg);
|
||||
for (const RegisterMaskPair &Use : RegOpers.Uses) {
|
||||
unsigned Reg = Use.RegUnit;
|
||||
LaneBitmask LiveMask = LiveRegs.contains(Reg);
|
||||
LaneBitmask LiveIn = Use.LaneMask & ~LiveMask;
|
||||
if (LiveIn != 0) {
|
||||
discoverLiveIn(RegisterMaskPair(Reg, LiveIn));
|
||||
increaseRegPressure(Reg, LiveMask, LiveMask | LiveIn);
|
||||
LiveRegs.insert(RegisterMaskPair(Reg, LiveIn));
|
||||
}
|
||||
// Kill liveness at last uses.
|
||||
LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
|
||||
if (LastUseMask != 0) {
|
||||
LiveRegs.erase(RegisterMaskPair(Reg, LastUseMask));
|
||||
decreaseRegPressure(Reg, LiveMask, LiveMask & ~LastUseMask);
|
||||
}
|
||||
if (lastUse && isLive) {
|
||||
LiveRegs.erase(Reg);
|
||||
decreaseRegPressure(Reg);
|
||||
} else if (!lastUse && !isLive)
|
||||
increaseRegPressure(Reg);
|
||||
}
|
||||
|
||||
// Generate liveness for defs.
|
||||
for (unsigned Reg : RegOpers.Defs) {
|
||||
if (LiveRegs.insert(Reg))
|
||||
increaseRegPressure(Reg);
|
||||
for (const RegisterMaskPair &Def : RegOpers.Defs) {
|
||||
LaneBitmask PreviousMask = LiveRegs.insert(Def);
|
||||
LaneBitmask NewMask = PreviousMask | Def.LaneMask;
|
||||
increaseRegPressure(Def.RegUnit, PreviousMask, NewMask);
|
||||
}
|
||||
|
||||
// Boost pressure for all dead defs together.
|
||||
increaseRegPressure(RegOpers.DeadDefs);
|
||||
decreaseRegPressure(RegOpers.DeadDefs);
|
||||
bumpDeadDefs(RegOpers.DeadDefs);
|
||||
|
||||
// Find the next instruction.
|
||||
do
|
||||
|
|
@ -728,22 +908,38 @@ static void computeMaxPressureDelta(ArrayRef<unsigned> OldMaxPressureVec,
|
|||
void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) {
|
||||
assert(!MI->isDebugValue() && "Expect a nondebug instruction.");
|
||||
|
||||
SlotIndex SlotIdx;
|
||||
if (RequireIntervals)
|
||||
SlotIdx = LIS->getInstructionIndex(MI).getRegSlot();
|
||||
|
||||
// Account for register pressure similar to RegPressureTracker::recede().
|
||||
RegisterOperands RegOpers;
|
||||
RegOpers.collect(*MI, *TRI, *MRI, /*IgnoreDead=*/true);
|
||||
RegOpers.collect(*MI, *TRI, *MRI, TrackLaneMasks, /*IgnoreDead=*/true);
|
||||
assert(RegOpers.DeadDefs.size() == 0);
|
||||
if (RequireIntervals)
|
||||
if (TrackLaneMasks)
|
||||
RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
|
||||
else if (RequireIntervals)
|
||||
RegOpers.detectDeadDefs(*MI, *LIS);
|
||||
|
||||
// Boost max pressure for all dead defs together.
|
||||
// Since CurrSetPressure and MaxSetPressure
|
||||
bumpDeadDefs(RegOpers.DeadDefs);
|
||||
|
||||
// Kill liveness at live defs.
|
||||
for (unsigned Reg : RegOpers.Defs) {
|
||||
if (!containsReg(RegOpers.Uses, Reg))
|
||||
decreaseRegPressure(Reg);
|
||||
for (const RegisterMaskPair &P : RegOpers.Defs) {
|
||||
unsigned Reg = P.RegUnit;
|
||||
LaneBitmask LiveLanes = LiveRegs.contains(Reg);
|
||||
LaneBitmask UseLanes = getRegLanes(RegOpers.Uses, Reg);
|
||||
LaneBitmask DefLanes = P.LaneMask;
|
||||
LaneBitmask LiveAfter = (LiveLanes & ~DefLanes) | UseLanes;
|
||||
decreaseRegPressure(Reg, LiveLanes, LiveAfter);
|
||||
}
|
||||
// Generate liveness for uses.
|
||||
for (unsigned Reg : RegOpers.Uses) {
|
||||
if (!LiveRegs.contains(Reg))
|
||||
increaseRegPressure(Reg);
|
||||
for (const RegisterMaskPair &P : RegOpers.Uses) {
|
||||
unsigned Reg = P.RegUnit;
|
||||
LaneBitmask LiveLanes = LiveRegs.contains(Reg);
|
||||
LaneBitmask LiveAfter = LiveLanes | P.LaneMask;
|
||||
increaseRegPressure(Reg, LiveLanes, LiveAfter);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -888,15 +1084,64 @@ getUpwardPressureDelta(const MachineInstr *MI, /*const*/ PressureDiff &PDiff,
|
|||
}
|
||||
|
||||
/// Helper to find a vreg use between two indices [PriorUseIdx, NextUseIdx).
|
||||
static bool findUseBetween(unsigned Reg, SlotIndex PriorUseIdx,
|
||||
SlotIndex NextUseIdx, const MachineRegisterInfo &MRI,
|
||||
const LiveIntervals *LIS) {
|
||||
for (const MachineInstr &MI : MRI.use_nodbg_instructions(Reg)) {
|
||||
SlotIndex InstSlot = LIS->getInstructionIndex(&MI).getRegSlot();
|
||||
if (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx)
|
||||
return true;
|
||||
/// The query starts with a lane bitmask which gets lanes/bits removed for every
|
||||
/// use we find.
|
||||
static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask,
|
||||
SlotIndex PriorUseIdx, SlotIndex NextUseIdx,
|
||||
const MachineRegisterInfo &MRI,
|
||||
const LiveIntervals *LIS) {
|
||||
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
|
||||
for (const MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
|
||||
if (MO.isUndef())
|
||||
continue;
|
||||
const MachineInstr *MI = MO.getParent();
|
||||
SlotIndex InstSlot = LIS->getInstructionIndex(MI).getRegSlot();
|
||||
if (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx) {
|
||||
unsigned SubRegIdx = MO.getSubReg();
|
||||
LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
|
||||
LastUseMask &= ~UseMask;
|
||||
if (LastUseMask == 0)
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
return LastUseMask;
|
||||
}
|
||||
|
||||
LaneBitmask RegPressureTracker::getLiveLanesAt(unsigned RegUnit,
|
||||
SlotIndex Pos) const {
|
||||
if (!RequireIntervals)
|
||||
return 0;
|
||||
|
||||
return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos,
|
||||
[](const LiveRange &LR, SlotIndex Pos) {
|
||||
return LR.liveAt(Pos);
|
||||
});
|
||||
}
|
||||
|
||||
LaneBitmask RegPressureTracker::getLastUsedLanes(unsigned RegUnit,
|
||||
SlotIndex Pos) const {
|
||||
if (!RequireIntervals)
|
||||
return 0;
|
||||
|
||||
return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit,
|
||||
Pos.getBaseIndex(),
|
||||
[](const LiveRange &LR, SlotIndex Pos) {
|
||||
const LiveRange::Segment *S = LR.getSegmentContaining(Pos);
|
||||
return S != nullptr && S->end == Pos.getRegSlot();
|
||||
});
|
||||
}
|
||||
|
||||
LaneBitmask RegPressureTracker::getLiveThroughAt(unsigned RegUnit,
|
||||
SlotIndex Pos) const {
|
||||
if (!RequireIntervals)
|
||||
return 0;
|
||||
|
||||
return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos,
|
||||
[](const LiveRange &LR, SlotIndex Pos) {
|
||||
const LiveRange::Segment *S = LR.getSegmentContaining(Pos);
|
||||
return S != nullptr && S->start < Pos.getRegSlot(true) &&
|
||||
S->end != Pos.getDeadSlot();
|
||||
});
|
||||
}
|
||||
|
||||
/// Record the downward impact of a single instruction on current register
|
||||
|
|
@ -908,39 +1153,49 @@ static bool findUseBetween(unsigned Reg, SlotIndex PriorUseIdx,
|
|||
void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
|
||||
assert(!MI->isDebugValue() && "Expect a nondebug instruction.");
|
||||
|
||||
// Account for register pressure similar to RegPressureTracker::recede().
|
||||
RegisterOperands RegOpers;
|
||||
RegOpers.collect(*MI, *TRI, *MRI);
|
||||
|
||||
// Kill liveness at last uses. Assume allocatable physregs are single-use
|
||||
// rather than checking LiveIntervals.
|
||||
SlotIndex SlotIdx;
|
||||
if (RequireIntervals)
|
||||
SlotIdx = LIS->getInstructionIndex(MI).getRegSlot();
|
||||
|
||||
for (unsigned Reg : RegOpers.Uses) {
|
||||
// Account for register pressure similar to RegPressureTracker::recede().
|
||||
RegisterOperands RegOpers;
|
||||
RegOpers.collect(*MI, *TRI, *MRI, TrackLaneMasks, false);
|
||||
if (TrackLaneMasks)
|
||||
RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
|
||||
|
||||
for (const RegisterMaskPair &Use : RegOpers.Uses) {
|
||||
unsigned Reg = Use.RegUnit;
|
||||
LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
|
||||
if (LastUseMask == 0)
|
||||
continue;
|
||||
if (RequireIntervals) {
|
||||
// The LastUseMask is queried from the liveness information of instruction
|
||||
// which may be further down the schedule. Some lanes may actually not be
|
||||
// last uses for the current position.
|
||||
// FIXME: allow the caller to pass in the list of vreg uses that remain
|
||||
// to be bottom-scheduled to avoid searching uses at each query.
|
||||
SlotIndex CurrIdx = getCurrSlot();
|
||||
const LiveRange *LR = getLiveRange(*LIS, Reg);
|
||||
if (LR) {
|
||||
LiveQueryResult LRQ = LR->Query(SlotIdx);
|
||||
if (LRQ.isKill() && !findUseBetween(Reg, CurrIdx, SlotIdx, *MRI, LIS))
|
||||
decreaseRegPressure(Reg);
|
||||
}
|
||||
} else if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
|
||||
// Allocatable physregs are always single-use before register rewriting.
|
||||
decreaseRegPressure(Reg);
|
||||
LastUseMask
|
||||
= findUseBetween(Reg, LastUseMask, CurrIdx, SlotIdx, *MRI, LIS);
|
||||
if (LastUseMask == 0)
|
||||
continue;
|
||||
}
|
||||
|
||||
LaneBitmask LiveMask = LiveRegs.contains(Reg);
|
||||
LaneBitmask NewMask = LiveMask & ~LastUseMask;
|
||||
decreaseRegPressure(Reg, LiveMask, NewMask);
|
||||
}
|
||||
|
||||
// Generate liveness for defs.
|
||||
increaseRegPressure(RegOpers.Defs);
|
||||
for (const RegisterMaskPair &Def : RegOpers.Defs) {
|
||||
unsigned Reg = Def.RegUnit;
|
||||
LaneBitmask LiveMask = LiveRegs.contains(Reg);
|
||||
LaneBitmask NewMask = LiveMask | Def.LaneMask;
|
||||
increaseRegPressure(Reg, LiveMask, NewMask);
|
||||
}
|
||||
|
||||
// Boost pressure for all dead defs together.
|
||||
increaseRegPressure(RegOpers.DeadDefs);
|
||||
decreaseRegPressure(RegOpers.DeadDefs);
|
||||
bumpDeadDefs(RegOpers.DeadDefs);
|
||||
}
|
||||
|
||||
/// Consider the pressure increase caused by traversing this instruction
|
||||
|
|
|
|||
|
|
@ -899,7 +899,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
|
|||
collectVRegUses(SU);
|
||||
|
||||
RegisterOperands RegOpers;
|
||||
RegOpers.collect(*MI, *TRI, MRI);
|
||||
RegOpers.collect(*MI, *TRI, MRI, TrackLaneMasks, false);
|
||||
if (PDiffs != nullptr)
|
||||
PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI);
|
||||
|
||||
|
|
|
|||
|
|
@ -327,9 +327,9 @@ void SIScheduleBlock::initRegPressure(MachineBasicBlock::iterator BeginBlock,
|
|||
BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
|
||||
|
||||
// Do not Track Physical Registers, because it messes up.
|
||||
for (unsigned Reg : RPTracker.getPressure().LiveInRegs) {
|
||||
if (TargetRegisterInfo::isVirtualRegister(Reg))
|
||||
LiveInRegs.insert(Reg);
|
||||
for (const auto &RegMaskPair : RPTracker.getPressure().LiveInRegs) {
|
||||
if (TargetRegisterInfo::isVirtualRegister(RegMaskPair.RegUnit))
|
||||
LiveInRegs.insert(RegMaskPair.RegUnit);
|
||||
}
|
||||
LiveOutRegs.clear();
|
||||
// There is several possibilities to distinguish:
|
||||
|
|
@ -354,7 +354,8 @@ void SIScheduleBlock::initRegPressure(MachineBasicBlock::iterator BeginBlock,
|
|||
// The RPTracker's LiveOutRegs has 1, 3, (some correct or incorrect)4, 5, 7
|
||||
// Comparing to LiveInRegs is not sufficient to differenciate 4 vs 5, 7
|
||||
// The use of findDefBetween removes the case 4.
|
||||
for (unsigned Reg : RPTracker.getPressure().LiveOutRegs) {
|
||||
for (const auto &RegMaskPair : RPTracker.getPressure().LiveOutRegs) {
|
||||
unsigned Reg = RegMaskPair.RegUnit;
|
||||
if (TargetRegisterInfo::isVirtualRegister(Reg) &&
|
||||
isDefBetween(Reg, LIS->getInstructionIndex(BeginBlock).getRegSlot(),
|
||||
LIS->getInstructionIndex(EndBlock).getRegSlot(),
|
||||
|
|
|
|||
|
|
@ -441,7 +441,7 @@ public:
|
|||
|
||||
// To init Block's RPTracker.
|
||||
void initRPTracker(RegPressureTracker &RPTracker) {
|
||||
RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
|
||||
RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false);
|
||||
}
|
||||
|
||||
MachineBasicBlock *getBB() { return BB; }
|
||||
|
|
@ -460,8 +460,10 @@ public:
|
|||
unsigned &VgprUsage,
|
||||
unsigned &SgprUsage);
|
||||
std::set<unsigned> getInRegs() {
|
||||
std::set<unsigned> InRegs (RPTracker.getPressure().LiveInRegs.begin(),
|
||||
RPTracker.getPressure().LiveInRegs.end());
|
||||
std::set<unsigned> InRegs;
|
||||
for (const auto &RegMaskPair : RPTracker.getPressure().LiveInRegs) {
|
||||
InRegs.insert(RegMaskPair.RegUnit);
|
||||
}
|
||||
return InRegs;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue