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[AArch64] Improve the Exynos M3 pipeline model 

llvm-svn: 349652
This commit is contained in:
Evandro Menezes 2018-12-19 17:37:51 +00:00
parent 1cfab9747d
commit 5d409b2278
2 changed files with 5 additions and 5 deletions
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8
llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
View File

@ -162,8 +162,8 @@ def M3WriteLE : SchedWriteRes<[M3UnitA,
let NumMicroOps = 2; }
def M3WriteLH : SchedWriteRes<[]> { let Latency = 5;
let NumMicroOps = 0; }
def M3WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M3WriteL5]>,
SchedVar<NoSchedPred, [M3WriteL4]>]>;
def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>,
SchedVar<NoSchedPred, [M3WriteL4]>]>;
def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; }
def M3WriteSA : SchedWriteRes<[M3UnitA,
@ -174,8 +174,8 @@ def M3WriteSB : SchedWriteRes<[M3UnitA,
M3UnitS]> { let Latency = 2;
let NumMicroOps = 2; }
def M3ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
SchedVar<NoSchedPred, [ReadDefault]>]>;
def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>,
SchedVar<NoSchedPred, [ReadDefault]>]>;
// Branch instructions.
def : SchedAlias<WriteBr, M3WriteZ0>;

2
llvm/test/tools/llvm-mca/AArch64/Exynos/load-register-offset.s
View File

@ -50,7 +50,7 @@
# EM1-NEXT: 1 5 1.00 * ldr d21, [x22, x23, lsl #3]
# EM1-NEXT: 2 6 2.00 * ldr q24, [x25, x26, lsl #4]
# EM3-NEXT: 1 5 0.50 * ldrb w0, [x1, x2, lsl #0]
# EM3-NEXT: 1 4 0.50 * ldrb w0, [x1, x2, lsl #0]
# EM3-NEXT: 1 5 0.50 * ldrh w3, [x4, x5, sxtx #1]
# EM3-NEXT: 2 5 0.50 * ldr w6, [x7, w8, uxtw #2]
# EM3-NEXT: 2 5 0.50 * ldr x9, [x10, w11, sxtw #3]