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[AVR] Fix build after r298178 

r298178 capitalized the fields in `ArgListEntry`.  All the official
targets were updated accordingly, but as an experimental target AVR
was missed.

llvm-svn: 298677
This commit is contained in:
Meador Inge 2017-03-24 01:57:29 +00:00
parent 49a6b6e91e
commit 5d3c599e82
1 changed files with 9 additions and 9 deletions
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18
llvm/lib/Target/AVR/AVRISelLowering.cpp
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@ -313,7 +313,7 @@ SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
unsigned Opcode = Op->getOpcode(); unsigned Opcode = Op->getOpcode();
assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
"Invalid opcode for Div/Rem lowering"); "Invalid opcode for Div/Rem lowering");
bool isSigned = (Opcode == ISD::SDIVREM); bool IsSigned = (Opcode == ISD::SDIVREM);
EVT VT = Op->getValueType(0); EVT VT = Op->getValueType(0);
Type *Ty = VT.getTypeForEVT(*DAG.getContext()); Type *Ty = VT.getTypeForEVT(*DAG.getContext());
@ -322,16 +322,16 @@ SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
default: default:
llvm_unreachable("Unexpected request for libcall!"); llvm_unreachable("Unexpected request for libcall!");
case MVT::i8: case MVT::i8:
LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
break; break;
case MVT::i16: case MVT::i16:
LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
break; break;
case MVT::i32: case MVT::i32:
LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
break; break;
case MVT::i64: case MVT::i64:
LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; LC = IsSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64;
break; break;
} }
@ -342,8 +342,8 @@ SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
for (SDValue const &Value : Op->op_values()) { for (SDValue const &Value : Op->op_values()) {
Entry.Node = Value; Entry.Node = Value;
Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext()); Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
Entry.isSExt = isSigned; Entry.IsSExt = IsSigned;
Entry.isZExt = !isSigned; Entry.IsZExt = !IsSigned;
Args.push_back(Entry); Args.push_back(Entry);
} }
@ -358,8 +358,8 @@ SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
.setChain(InChain) .setChain(InChain)
.setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
.setInRegister() .setInRegister()
.setSExtResult(isSigned) .setSExtResult(IsSigned)
.setZExtResult(!isSigned); .setZExtResult(!IsSigned);
std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
return CallInfo.first; return CallInfo.first;