From 5d31f6945b21fb462cdcbc08b7c0656281a23835 Mon Sep 17 00:00:00 2001 From: Ana Pazos Date: Thu, 23 Jan 2014 19:18:57 +0000 Subject: [PATCH] [AArch64] Added vselect patterns with float and double types llvm-svn: 199925 --- llvm/lib/Target/AArch64/AArch64InstrNEON.td | 4 ++++ llvm/test/CodeGen/AArch64/neon-bsl.ll | 13 +++++++++++++ 2 files changed, 17 insertions(+) diff --git a/llvm/lib/Target/AArch64/AArch64InstrNEON.td b/llvm/lib/Target/AArch64/AArch64InstrNEON.td index 3f9743989b5a..c673b3adc9d3 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrNEON.td +++ b/llvm/lib/Target/AArch64/AArch64InstrNEON.td @@ -473,6 +473,10 @@ multiclass Neon_bitwise3V_patterns; def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)), (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>; + def : Pat<(v2f64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)), + (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>; + def : Pat<(v4f32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)), + (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>; // Allow to match BSL instruction pattern with non-constant operand def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd), diff --git a/llvm/test/CodeGen/AArch64/neon-bsl.ll b/llvm/test/CodeGen/AArch64/neon-bsl.ll index 6bd923dc2cca..c55fd01320bb 100644 --- a/llvm/test/CodeGen/AArch64/neon-bsl.ll +++ b/llvm/test/CodeGen/AArch64/neon-bsl.ll @@ -220,3 +220,16 @@ entry: ret <2 x double> %vbsl3.i } +define <2 x double> @test_bsl_v2f64(<2 x i1> %v1, <2 x double> %v2, <2 x double> %v3) { +; CHECK-LABEL: test_bsl_v2f64: +; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b + %1 = select <2 x i1> %v1, <2 x double> %v2, <2 x double> %v3 + ret <2 x double> %1 +} + +define <4 x float> @test_bsl_v4f32(<4 x i1> %v1, <4 x float> %v2, <4 x float> %v3) { +; CHECK-LABEL: test_bsl_v4f32: +; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b + %1 = select <4 x i1> %v1, <4 x float> %v2, <4 x float> %v3 + ret <4 x float> %1 +}