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[x86] prevent infinite looping from vselect commutation (PR41066) 

This is an immediate fix for:
https://bugs.llvm.org/show_bug.cgi?id=41066
...but as noted there and the code comments, we should do better
by stubbing this out sooner.

llvm-svn: 356158
This commit is contained in:
Sanjay Patel 2019-03-14 15:32:34 +00:00
parent 4b1a509924
commit 5d1df114e8
2 changed files with 27 additions and 6 deletions
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14
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -34559,11 +34559,15 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
assert(CondVT.isVector() && "Vector select expects a vector selector!"); assert(CondVT.isVector() && "Vector select expects a vector selector!");
bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
// Check if the first operand is all zeros and Cond type is vXi1. // Check if the first operand is all zeros and Cond type is vXi1.
// This situation only applies to avx512. // This situation only applies to avx512.
if (TValIsAllZeros && Subtarget.hasAVX512() && Cond.hasOneUse() && // TODO: Use isNullOrNullSplat() to distinguish constants with undefs?
CondVT.getVectorElementType() == MVT::i1) { // TODO: Can we assert that both operands are not zeros (because that should
// get simplified at node creation time)?
bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
if (TValIsAllZeros && !FValIsAllZeros && Subtarget.hasAVX512() &&
Cond.hasOneUse() && CondVT.getVectorElementType() == MVT::i1) {
// Invert the cond to not(cond) : xor(op,allones)=not(op) // Invert the cond to not(cond) : xor(op,allones)=not(op)
SDValue CondNew = DAG.getNOT(DL, Cond, CondVT); SDValue CondNew = DAG.getNOT(DL, Cond, CondVT);
// Vselect cond, op1, op2 = Vselect not(cond), op2, op1 // Vselect cond, op1, op2 = Vselect not(cond), op2, op1
@ -34578,11 +34582,9 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
if (CondVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) if (CondVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
return SDValue(); return SDValue();
bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
// Try to invert the condition if true value is not all 1s and false value is // Try to invert the condition if true value is not all 1s and false value is
// not all 0s. Only do this if the condition has one use. // not all 0s. Only do this if the condition has one use.
bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
if (!TValIsAllOnes && !FValIsAllZeros && Cond.hasOneUse() && if (!TValIsAllOnes && !FValIsAllZeros && Cond.hasOneUse() &&
// Check if the selector will be produced by CMPP*/PCMP*. // Check if the selector will be produced by CMPP*/PCMP*.
Cond.getOpcode() == ISD::SETCC && Cond.getOpcode() == ISD::SETCC &&

19
llvm/test/CodeGen/X86/avx512-vec-cmp.ll
View File

@ -1108,3 +1108,22 @@ define i16 @pcmpeq_mem_2(<16 x i32> %a, <16 x i32>* %b) {
%cast = bitcast <16 x i1> %cmp to i16 %cast = bitcast <16 x i1> %cmp to i16
ret i16 %cast ret i16 %cast
} }
; Don't let a degenerate case trigger an infinite loop.
; This should get simplified before it even exists as a vselect node,
; but that does not happen as of this change.
define <2 x i64> @PR41066(<2 x i64> %t0, <2 x double> %x, <2 x double> %y) {
; AVX512-LABEL: PR41066:
; AVX512: ## %bb.0:
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x57,0xc0]
; AVX512-NEXT: retq ## encoding: [0xc3]
;
; SKX-LABEL: PR41066:
; SKX: ## %bb.0:
; SKX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x57,0xc0]
; SKX-NEXT: retq ## encoding: [0xc3]
%t1 = fcmp ogt <2 x double> %x, %y
%t2 = select <2 x i1> %t1, <2 x i64> <i64 undef, i64 0>, <2 x i64> zeroinitializer
ret <2 x i64> %t2
}