forked from OSchip/llvm-project
[mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generator
Differential Revision: http://reviews.llvm.org/D7611 llvm-svn: 229845
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@ -1154,12 +1154,14 @@ def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
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def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
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def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
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def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
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ADD_FM<0, 0x24>;
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def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
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ADD_FM<0, 0x25>;
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def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
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ADD_FM<0, 0x26>;
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}
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def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
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/// Shift Instructions
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@ -0,0 +1,18 @@
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
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; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
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define i32 @main() {
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entry:
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%retval = alloca i32, align 4
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = load i32* %b, align 4
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%1 = load i32* %c, align 4
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%and = and i32 %0, %1
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store i32 %and, i32* %a, align 4
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ret i32 0
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}
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; CHECK: and16
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@ -0,0 +1,18 @@
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
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; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
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define i32 @main() {
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entry:
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%retval = alloca i32, align 4
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = load i32* %b, align 4
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%1 = load i32* %c, align 4
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%or = or i32 %0, %1
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store i32 %or, i32* %a, align 4
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ret i32 0
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}
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; CHECK: or16
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@ -0,0 +1,18 @@
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
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; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
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define i32 @main() {
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entry:
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%retval = alloca i32, align 4
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = load i32* %b, align 4
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%1 = load i32* %c, align 4
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%xor = xor i32 %0, %1
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store i32 %xor, i32* %a, align 4
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ret i32 0
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}
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; CHECK: xor16
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