forked from OSchip/llvm-project
[llvm][AArch64] Add missing FPCR, H and B registers to Codeview mapping
Fixes https://github.com/llvm/llvm-project/issues/56484
H registers are 16 bit views of AArch64's Neon registers and
B are the 8 bit views.
msvc does not support 16 bit float (some mention in DirectX but I
couldn't find a way to get to it) so for lack of a better reference
I'm using:
85c9b41b33/server/references/dia/include/cvconst.h
(the other microsoft-pdb repo is no longer up to date)
Luckily clang does support fp16 so a test is added for that.
There is no 8 bit float type so I had to get creative with the
test case. We're not testing for correct debug info here just
that we can select the B register and not crash in the process.
For FPCR it's never going to be passed as an argument so I've
not added a test for it. It is included to keep our list looking
the same as the reference.
Reviewed By: majnemer
Differential Revision: https://reviews.llvm.org/D129774
This commit is contained in:
David Spickett
parent
e717f91c96
commit
5d14873249
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@ -523,10 +523,12 @@ CV_REGISTER(ARM_NQ15, 415)
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#if defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_ARM64)
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// arm64intr.h from MSVC defines ARM64_FPSR, which conflicts with
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// arm64intr.h from MSVC defines ARM64_FPSR and ARM64_FPCR, which conflicts with
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// these declarations.
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#pragma push_macro("ARM64_FPSR")
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#pragma push_macro("ARM64_FPCR")
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#undef ARM64_FPSR
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#undef ARM64_FPCR
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// ARM64 registers
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@ -715,7 +717,79 @@ CV_REGISTER(ARM64_Q31, 211)
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// Floating point status register
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CV_REGISTER(ARM64_FPSR, 220)
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CV_REGISTER(ARM64_FPCR, 221)
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// 8 bit floating point registers
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CV_REGISTER(ARM64_B0, 230)
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CV_REGISTER(ARM64_B1, 231)
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CV_REGISTER(ARM64_B2, 232)
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CV_REGISTER(ARM64_B3, 233)
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CV_REGISTER(ARM64_B4, 234)
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CV_REGISTER(ARM64_B5, 235)
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CV_REGISTER(ARM64_B6, 236)
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CV_REGISTER(ARM64_B7, 237)
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CV_REGISTER(ARM64_B8, 238)
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CV_REGISTER(ARM64_B9, 239)
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CV_REGISTER(ARM64_B10, 240)
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CV_REGISTER(ARM64_B11, 241)
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CV_REGISTER(ARM64_B12, 242)
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CV_REGISTER(ARM64_B13, 243)
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CV_REGISTER(ARM64_B14, 244)
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CV_REGISTER(ARM64_B15, 245)
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CV_REGISTER(ARM64_B16, 246)
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CV_REGISTER(ARM64_B17, 247)
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CV_REGISTER(ARM64_B18, 248)
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CV_REGISTER(ARM64_B19, 249)
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CV_REGISTER(ARM64_B20, 250)
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CV_REGISTER(ARM64_B21, 251)
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CV_REGISTER(ARM64_B22, 252)
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CV_REGISTER(ARM64_B23, 253)
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CV_REGISTER(ARM64_B24, 254)
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CV_REGISTER(ARM64_B25, 255)
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CV_REGISTER(ARM64_B26, 256)
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CV_REGISTER(ARM64_B27, 257)
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CV_REGISTER(ARM64_B28, 258)
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CV_REGISTER(ARM64_B29, 259)
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CV_REGISTER(ARM64_B30, 260)
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CV_REGISTER(ARM64_B31, 261)
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// 16 bit floating point registers
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CV_REGISTER(ARM64_H0, 270)
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CV_REGISTER(ARM64_H1, 271)
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CV_REGISTER(ARM64_H2, 272)
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CV_REGISTER(ARM64_H3, 273)
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CV_REGISTER(ARM64_H4, 274)
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CV_REGISTER(ARM64_H5, 275)
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CV_REGISTER(ARM64_H6, 276)
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CV_REGISTER(ARM64_H7, 277)
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CV_REGISTER(ARM64_H8, 278)
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CV_REGISTER(ARM64_H9, 279)
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CV_REGISTER(ARM64_H10, 280)
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CV_REGISTER(ARM64_H11, 281)
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CV_REGISTER(ARM64_H12, 282)
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CV_REGISTER(ARM64_H13, 283)
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CV_REGISTER(ARM64_H14, 284)
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CV_REGISTER(ARM64_H15, 285)
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CV_REGISTER(ARM64_H16, 286)
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CV_REGISTER(ARM64_H17, 287)
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CV_REGISTER(ARM64_H18, 288)
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CV_REGISTER(ARM64_H19, 289)
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CV_REGISTER(ARM64_H20, 290)
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CV_REGISTER(ARM64_H21, 291)
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CV_REGISTER(ARM64_H22, 292)
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CV_REGISTER(ARM64_H23, 293)
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CV_REGISTER(ARM64_H24, 294)
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CV_REGISTER(ARM64_H25, 295)
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CV_REGISTER(ARM64_H26, 296)
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CV_REGISTER(ARM64_H27, 297)
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CV_REGISTER(ARM64_H28, 298)
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CV_REGISTER(ARM64_H29, 299)
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CV_REGISTER(ARM64_H30, 300)
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CV_REGISTER(ARM64_H31, 301)
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#pragma pop_macro("ARM64_FPSR")
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#pragma pop_macro("ARM64_FPCR")
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#endif // defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_ARM64)
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@ -231,7 +231,70 @@ void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
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{codeview::RegisterId::ARM64_Q29, AArch64::Q29},
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{codeview::RegisterId::ARM64_Q30, AArch64::Q30},
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{codeview::RegisterId::ARM64_Q31, AArch64::Q31},
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{codeview::RegisterId::ARM64_B0, AArch64::B0},
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{codeview::RegisterId::ARM64_B1, AArch64::B1},
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{codeview::RegisterId::ARM64_B2, AArch64::B2},
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{codeview::RegisterId::ARM64_B3, AArch64::B3},
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{codeview::RegisterId::ARM64_B4, AArch64::B4},
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{codeview::RegisterId::ARM64_B5, AArch64::B5},
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{codeview::RegisterId::ARM64_B6, AArch64::B6},
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{codeview::RegisterId::ARM64_B7, AArch64::B7},
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{codeview::RegisterId::ARM64_B8, AArch64::B8},
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{codeview::RegisterId::ARM64_B9, AArch64::B9},
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{codeview::RegisterId::ARM64_B10, AArch64::B10},
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{codeview::RegisterId::ARM64_B11, AArch64::B11},
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{codeview::RegisterId::ARM64_B12, AArch64::B12},
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{codeview::RegisterId::ARM64_B13, AArch64::B13},
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{codeview::RegisterId::ARM64_B14, AArch64::B14},
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{codeview::RegisterId::ARM64_B15, AArch64::B15},
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{codeview::RegisterId::ARM64_B16, AArch64::B16},
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{codeview::RegisterId::ARM64_B17, AArch64::B17},
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{codeview::RegisterId::ARM64_B18, AArch64::B18},
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{codeview::RegisterId::ARM64_B19, AArch64::B19},
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{codeview::RegisterId::ARM64_B20, AArch64::B20},
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{codeview::RegisterId::ARM64_B21, AArch64::B21},
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{codeview::RegisterId::ARM64_B22, AArch64::B22},
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{codeview::RegisterId::ARM64_B23, AArch64::B23},
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{codeview::RegisterId::ARM64_B24, AArch64::B24},
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{codeview::RegisterId::ARM64_B25, AArch64::B25},
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{codeview::RegisterId::ARM64_B26, AArch64::B26},
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{codeview::RegisterId::ARM64_B27, AArch64::B27},
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{codeview::RegisterId::ARM64_B28, AArch64::B28},
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{codeview::RegisterId::ARM64_B29, AArch64::B29},
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{codeview::RegisterId::ARM64_B30, AArch64::B30},
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{codeview::RegisterId::ARM64_B31, AArch64::B31},
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{codeview::RegisterId::ARM64_H0, AArch64::H0},
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{codeview::RegisterId::ARM64_H1, AArch64::H1},
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{codeview::RegisterId::ARM64_H2, AArch64::H2},
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{codeview::RegisterId::ARM64_H3, AArch64::H3},
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{codeview::RegisterId::ARM64_H4, AArch64::H4},
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{codeview::RegisterId::ARM64_H5, AArch64::H5},
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{codeview::RegisterId::ARM64_H6, AArch64::H6},
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{codeview::RegisterId::ARM64_H7, AArch64::H7},
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{codeview::RegisterId::ARM64_H8, AArch64::H8},
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{codeview::RegisterId::ARM64_H9, AArch64::H9},
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{codeview::RegisterId::ARM64_H10, AArch64::H10},
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{codeview::RegisterId::ARM64_H11, AArch64::H11},
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{codeview::RegisterId::ARM64_H12, AArch64::H12},
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{codeview::RegisterId::ARM64_H13, AArch64::H13},
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{codeview::RegisterId::ARM64_H14, AArch64::H14},
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{codeview::RegisterId::ARM64_H15, AArch64::H15},
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{codeview::RegisterId::ARM64_H16, AArch64::H16},
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{codeview::RegisterId::ARM64_H17, AArch64::H17},
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{codeview::RegisterId::ARM64_H18, AArch64::H18},
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{codeview::RegisterId::ARM64_H19, AArch64::H19},
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{codeview::RegisterId::ARM64_H20, AArch64::H20},
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{codeview::RegisterId::ARM64_H21, AArch64::H21},
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{codeview::RegisterId::ARM64_H22, AArch64::H22},
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{codeview::RegisterId::ARM64_H23, AArch64::H23},
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{codeview::RegisterId::ARM64_H24, AArch64::H24},
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{codeview::RegisterId::ARM64_H25, AArch64::H25},
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{codeview::RegisterId::ARM64_H26, AArch64::H26},
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{codeview::RegisterId::ARM64_H27, AArch64::H27},
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{codeview::RegisterId::ARM64_H28, AArch64::H28},
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{codeview::RegisterId::ARM64_H29, AArch64::H29},
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{codeview::RegisterId::ARM64_H30, AArch64::H30},
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{codeview::RegisterId::ARM64_H31, AArch64::H31},
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};
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for (const auto &I : RegMap)
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MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
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@ -0,0 +1,72 @@
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# This test checks that we have a mapping between the B registers and their Codeview numbers.
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# There is no 8 bit float type so this is a modified version of codeview-h-register.mir to
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# have a B register in the location info but not the instructions. Which is incorrect
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# but in ways this test does not care about.
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#
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# RUN: llc %s -mtriple=arm64-windows -filetype=obj -o %t --start-after=unpack-mi-bundles
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# RUN: llvm-readobj --codeview %t | FileCheck %s --check-prefix=OBJ
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#
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# OBJ: LocalSym {
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# OBJ: Kind: S_LOCAL (0x113E)
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# OBJ: Type: __half (0x46)
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# OBJ: Flags [ (0x1)
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# OBJ: IsParameter (0x1)
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# OBJ: ]
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# OBJ: VarName: x
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# OBJ: }
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# OBJ: DefRangeRegisterSym {
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# OBJ: Kind: S_DEFRANGE_REGISTER (0x1141)
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# OBJ: Register: ARM64_B0 (0xE6)
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# OBJ: MayHaveNoName: 0
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# OBJ: LocalVariableAddrRange {
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# OBJ: OffsetStart: .text+0x0
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# OBJ: ISectStart: 0x0
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# OBJ: Range: 0x4
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# OBJ: }
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# OBJ: }
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#
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--- |
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define internal fastcc i1 @test.fn(half %0) !dbg !4 {
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Entry:
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call void @llvm.dbg.value(metadata half %0, metadata !11, metadata !DIExpression()), !dbg !13
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%1 = fcmp une half 0xH0000, %0, !dbg !14
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ret i1 %1
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}
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; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
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declare void @llvm.dbg.value(metadata, metadata, metadata) #0
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attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
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!llvm.module.flags = !{!0, !1}
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!llvm.dbg.cu = !{!2}
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!0 = !{i32 2, !"Debug Info Version", i32 3}
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!1 = !{i32 2, !"CodeView", i32 1}
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!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug)
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!3 = !DIFile(filename: "test", directory: ".")
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!4 = distinct !DISubprogram(name: "fn", linkageName: "test.fn", scope: !5, file: !5, line: 32, type: !6, scopeLine: 32, flags: DIFlagStaticMember, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !2, retainedNodes: !10)
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!5 = !DIFile(filename: "test.o", directory: ".")
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!6 = !DISubroutineType(types: !7)
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!7 = !{!8, !9}
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!8 = !DIBasicType(name: "bool", size: 1, encoding: DW_ATE_boolean)
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!9 = !DIBasicType(name: "f16", size: 16, encoding: DW_ATE_float)
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!10 = !{!11}
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!11 = !DILocalVariable(name: "x", arg: 1, scope: !12, file: !5, line: 32, type: !9)
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!12 = distinct !DILexicalBlock(scope: !4, file: !5, line: 32, column: 1)
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!13 = !DILocation(line: 32, column: 31, scope: !12)
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!14 = !DILocation(line: 33, column: 5, scope: !15)
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!15 = distinct !DILexicalBlock(scope: !12, file: !5)
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...
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---
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name: test.fn
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body: |
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bb.0:
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liveins: $b0
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DBG_VALUE $b0, $noreg, !11, !DIExpression(), debug-location !13
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renamable $s0 = nofpexcept FCVTSHr killed renamable $h0, debug-location !14
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DBG_VALUE $b0, $noreg, !11, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !13
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nofpexcept FCMPSri killed renamable $s0, implicit-def $nzcv, debug-location !14
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renamable $w0 = CSINCWr $wzr, $wzr, 0, implicit killed $nzcv, debug-location !14
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RET undef $lr, implicit killed $w0
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...
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@ -0,0 +1,70 @@
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# This test checks that we have a mapping between the H register chosen by codegen
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# and the codeview number for that register.
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#
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# RUN: llc %s -mtriple=arm64-windows -filetype=obj -o %t --start-after=unpack-mi-bundles
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# RUN: llvm-readobj --codeview %t | FileCheck %s --check-prefix=OBJ
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#
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# OBJ: LocalSym {
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# OBJ: Kind: S_LOCAL (0x113E)
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# OBJ: Type: __half (0x46)
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# OBJ: Flags [ (0x1)
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# OBJ: IsParameter (0x1)
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# OBJ: ]
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# OBJ: VarName: x
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# OBJ: }
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# OBJ: DefRangeRegisterSym {
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# OBJ: Kind: S_DEFRANGE_REGISTER (0x1141)
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# OBJ: Register: ARM64_H0 (0x10E)
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# OBJ: MayHaveNoName: 0
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# OBJ: LocalVariableAddrRange {
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# OBJ: OffsetStart: .text+0x0
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# OBJ: ISectStart: 0x0
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# OBJ: Range: 0x4
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# OBJ: }
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# OBJ: }
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#
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--- |
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define internal fastcc i1 @test.fn(half %0) !dbg !4 {
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Entry:
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call void @llvm.dbg.value(metadata half %0, metadata !11, metadata !DIExpression()), !dbg !13
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%1 = fcmp une half 0xH0000, %0, !dbg !14
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ret i1 %1
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}
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; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
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declare void @llvm.dbg.value(metadata, metadata, metadata) #0
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attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
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!llvm.module.flags = !{!0, !1}
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!llvm.dbg.cu = !{!2}
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!0 = !{i32 2, !"Debug Info Version", i32 3}
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!1 = !{i32 2, !"CodeView", i32 1}
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!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug)
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!3 = !DIFile(filename: "test", directory: ".")
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!4 = distinct !DISubprogram(name: "fn", linkageName: "test.fn", scope: !5, file: !5, line: 32, type: !6, scopeLine: 32, flags: DIFlagStaticMember, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !2, retainedNodes: !10)
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!5 = !DIFile(filename: "test.o", directory: ".")
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!6 = !DISubroutineType(types: !7)
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!7 = !{!8, !9}
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!8 = !DIBasicType(name: "bool", size: 1, encoding: DW_ATE_boolean)
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!9 = !DIBasicType(name: "f16", size: 16, encoding: DW_ATE_float)
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!10 = !{!11}
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!11 = !DILocalVariable(name: "x", arg: 1, scope: !12, file: !5, line: 32, type: !9)
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!12 = distinct !DILexicalBlock(scope: !4, file: !5, line: 32, column: 1)
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!13 = !DILocation(line: 32, column: 31, scope: !12)
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!14 = !DILocation(line: 33, column: 5, scope: !15)
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!15 = distinct !DILexicalBlock(scope: !12, file: !5)
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...
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---
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name: test.fn
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body: |
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bb.0:
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liveins: $h0
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DBG_VALUE $h0, $noreg, !11, !DIExpression(), debug-location !13
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renamable $s0 = nofpexcept FCVTSHr killed renamable $h0, debug-location !14
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DBG_VALUE $h0, $noreg, !11, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !13
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nofpexcept FCMPSri killed renamable $s0, implicit-def $nzcv, debug-location !14
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renamable $w0 = CSINCWr $wzr, $wzr, 0, implicit killed $nzcv, debug-location !14
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RET undef $lr, implicit killed $w0
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...
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