forked from OSchip/llvm-project
[RISCV] Add codegen support for RV32D floating point arithmetic operations
llvm-svn: 329874
This commit is contained in:
Alex Bradbury
parent
dfaa021e99
commit
5d0dfa5e0e
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@ -121,8 +121,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::BR_CC, MVT::f32, Expand);
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}
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if (Subtarget.hasStdExtD())
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if (Subtarget.hasStdExtD()) {
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setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
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setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
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setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
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}
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setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
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setOperationAction(ISD::BlockAddress, XLenVT, Custom);
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@ -191,6 +191,9 @@ def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst>
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: Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>;
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class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
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: Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>;
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@ -199,6 +202,32 @@ let Predicates = [HasStdExtD] in {
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/// Float arithmetic operations
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def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
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def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
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def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
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def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>;
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def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
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def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
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def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
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def : PatFpr64Fpr64<fcopysign, FSGNJ_D>;
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def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
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// The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the
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// canonical NaN when giving a signaling NaN. This doesn't match the LLVM
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// behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the
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// draft 2.3 ISA spec changes the definition of fmin and fmax in a way that
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// matches LLVM's fminnum and fmaxnum
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// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
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def : PatFpr64Fpr64<fminnum, FMIN_D>;
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def : PatFpr64Fpr64<fmaxnum, FMAX_D>;
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/// Setcc
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def : PatFpr64Fpr64<setoeq, FEQ_D>;
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def : PatFpr64Fpr64<setolt, FLT_D>;
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def : PatFpr64Fpr64<setole, FLE_D>;
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/// Loads
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@ -21,3 +21,259 @@ define double @fadd_d(double %a, double %b) nounwind {
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%1 = fadd double %a, %b
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ret double %1
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}
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define double @fsub_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fsub_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fsub.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = fsub double %a, %b
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ret double %1
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}
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define double @fmul_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fmul_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fmul.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = fmul double %a, %b
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ret double %1
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}
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define double @fdiv_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fdiv_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fdiv.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = fdiv double %a, %b
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ret double %1
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}
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declare double @llvm.sqrt.f32(double)
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define double @fsqrt_d(double %a) nounwind {
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; RV32IFD-LABEL: fsqrt_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: fsqrt.d ft0, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = call double @llvm.sqrt.f32(double %a)
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ret double %1
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}
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declare double @llvm.copysign.f32(double, double)
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define double @fsgnj_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fsgnj_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fsgnj.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = call double @llvm.copysign.f32(double %a, double %b)
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ret double %1
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}
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define double @fneg_d(double %a) nounwind {
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; RV32IFD-LABEL: fneg_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: fneg.d ft0, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = fsub double -0.0, %a
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ret double %1
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}
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define double @fsgnjn_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fsgnjn_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fsgnjn.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = fsub double -0.0, %b
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%2 = call double @llvm.copysign.f32(double %a, double %1)
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ret double %2
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}
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declare double @llvm.fabs.f32(double)
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define double @fabs_d(double %a) nounwind {
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; RV32IFD-LABEL: fabs_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: fabs.d ft0, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = call double @llvm.fabs.f32(double %a)
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ret double %1
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}
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declare double @llvm.minnum.f32(double, double)
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define double @fmin_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fmin_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fmin.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = call double @llvm.minnum.f32(double %a, double %b)
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ret double %1
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}
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declare double @llvm.maxnum.f32(double, double)
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define double @fmax_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fmax_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fmax.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = call double @llvm.maxnum.f32(double %a, double %b)
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ret double %1
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}
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define i32 @feq_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: feq_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: feq.d a0, ft1, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = fcmp oeq double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @flt_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: flt_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: flt.d a0, ft1, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = fcmp olt double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fle_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fle_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fle.d a0, ft1, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = fcmp ole double %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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