forked from OSchip/llvm-project
[PowerPC] Support non-direct-sub/superclass VSX copies
Our register allocation has become better recently, it seems, and is now starting to generate cross-block copies into inflated register classes. These copies are not transformed into subregister insertions/extractions by the PPCVSXCopy class, and so need to be handled directly by PPCInstrInfo::copyPhysReg. The code to do this was *almost* there, but not quite (it was unnecessarily restricting itself to only the direct sub/super-register-class case (not copying between, for example, something in VRRC and the lower-half of VSRC which are super-registers of F8RC). Triggering this behavior manually is difficult; I'm including two bugpoint-reduced test cases from the test suite. llvm-svn: 229457
This commit is contained in:
Hal Finkel
parent
fcb2de694a
commit
5cedafb8cd
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@ -699,7 +699,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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// legalization. Promote them here.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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if (PPC::F8RCRegClass.contains(DestReg) &&
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PPC::VSLRCRegClass.contains(SrcReg)) {
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PPC::VSRCRegClass.contains(SrcReg)) {
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unsigned SuperReg =
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TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
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@ -708,7 +708,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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DestReg = SuperReg;
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} else if (PPC::VRRCRegClass.contains(DestReg) &&
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PPC::VSHRCRegClass.contains(SrcReg)) {
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PPC::VSRCRegClass.contains(SrcReg)) {
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unsigned SuperReg =
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TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
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@ -717,7 +717,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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DestReg = SuperReg;
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} else if (PPC::F8RCRegClass.contains(SrcReg) &&
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PPC::VSLRCRegClass.contains(DestReg)) {
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PPC::VSRCRegClass.contains(DestReg)) {
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unsigned SuperReg =
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TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
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@ -726,7 +726,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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SrcReg = SuperReg;
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} else if (PPC::VRRCRegClass.contains(SrcReg) &&
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PPC::VSHRCRegClass.contains(DestReg)) {
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PPC::VSRCRegClass.contains(DestReg)) {
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unsigned SuperReg =
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TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
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@ -0,0 +1,133 @@
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; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@ub = external global [1024 x i32], align 4
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@uc = external global [1024 x i32], align 4
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; Function Attrs: noinline nounwind
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define void @_Z8example9Pj() #0 {
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entry:
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br label %vector.body
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; CHECK-LABEL: @_Z8example9Pj
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; CHECK: xxlor
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vector.body: ; preds = %vector.body, %entry
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %43, %vector.body ]
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%vec.phi20 = phi <4 x i32> [ zeroinitializer, %entry ], [ %44, %vector.body ]
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%vec.phi21 = phi <4 x i32> [ zeroinitializer, %entry ], [ %45, %vector.body ]
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%vec.phi23 = phi <4 x i32> [ zeroinitializer, %entry ], [ %46, %vector.body ]
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%vec.phi24 = phi <4 x i32> [ zeroinitializer, %entry ], [ %47, %vector.body ]
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%vec.phi25 = phi <4 x i32> [ zeroinitializer, %entry ], [ %48, %vector.body ]
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%vec.phi26 = phi <4 x i32> [ zeroinitializer, %entry ], [ %49, %vector.body ]
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%vec.phi27 = phi <4 x i32> [ zeroinitializer, %entry ], [ %50, %vector.body ]
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%vec.phi28 = phi <4 x i32> [ zeroinitializer, %entry ], [ %51, %vector.body ]
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%vec.phi29 = phi <4 x i32> [ zeroinitializer, %entry ], [ %52, %vector.body ]
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%vec.phi30 = phi <4 x i32> [ zeroinitializer, %entry ], [ %53, %vector.body ]
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%wide.load32 = load <4 x i32>* null, align 4
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%.sum82 = add i64 %index, 24
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%0 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum82
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%1 = bitcast i32* %0 to <4 x i32>*
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%wide.load36 = load <4 x i32>* %1, align 4
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%wide.load37 = load <4 x i32>* undef, align 4
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%.sum84 = add i64 %index, 32
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%2 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum84
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%3 = bitcast i32* %2 to <4 x i32>*
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%wide.load38 = load <4 x i32>* %3, align 4
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%.sum85 = add i64 %index, 36
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%4 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum85
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%5 = bitcast i32* %4 to <4 x i32>*
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%wide.load39 = load <4 x i32>* %5, align 4
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%6 = getelementptr [1024 x i32]* @ub, i64 0, i64 undef
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%7 = bitcast i32* %6 to <4 x i32>*
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%wide.load40 = load <4 x i32>* %7, align 4
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%.sum87 = add i64 %index, 44
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%8 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum87
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%9 = bitcast i32* %8 to <4 x i32>*
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%wide.load41 = load <4 x i32>* %9, align 4
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%10 = getelementptr inbounds [1024 x i32]* @uc, i64 0, i64 %index
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%11 = bitcast i32* %10 to <4 x i32>*
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%wide.load42 = load <4 x i32>* %11, align 4
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%.sum8889 = or i64 %index, 4
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%12 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum8889
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%13 = bitcast i32* %12 to <4 x i32>*
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%wide.load43 = load <4 x i32>* %13, align 4
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%.sum9091 = or i64 %index, 8
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%14 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum9091
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%15 = bitcast i32* %14 to <4 x i32>*
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%wide.load44 = load <4 x i32>* %15, align 4
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%.sum94 = add i64 %index, 16
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%16 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum94
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%17 = bitcast i32* %16 to <4 x i32>*
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%wide.load46 = load <4 x i32>* %17, align 4
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%.sum95 = add i64 %index, 20
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%18 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum95
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%19 = bitcast i32* %18 to <4 x i32>*
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%wide.load47 = load <4 x i32>* %19, align 4
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%20 = getelementptr [1024 x i32]* @uc, i64 0, i64 undef
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%21 = bitcast i32* %20 to <4 x i32>*
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%wide.load48 = load <4 x i32>* %21, align 4
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%.sum97 = add i64 %index, 28
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%22 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum97
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%23 = bitcast i32* %22 to <4 x i32>*
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%wide.load49 = load <4 x i32>* %23, align 4
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%.sum98 = add i64 %index, 32
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%24 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum98
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%25 = bitcast i32* %24 to <4 x i32>*
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%wide.load50 = load <4 x i32>* %25, align 4
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%.sum99 = add i64 %index, 36
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%26 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum99
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%27 = bitcast i32* %26 to <4 x i32>*
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%wide.load51 = load <4 x i32>* %27, align 4
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%.sum100 = add i64 %index, 40
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%28 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum100
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%29 = bitcast i32* %28 to <4 x i32>*
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%wide.load52 = load <4 x i32>* %29, align 4
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%.sum101 = add i64 %index, 44
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%30 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum101
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%31 = bitcast i32* %30 to <4 x i32>*
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%wide.load53 = load <4 x i32>* %31, align 4
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%32 = add <4 x i32> zeroinitializer, %vec.phi
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%33 = add <4 x i32> zeroinitializer, %vec.phi20
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%34 = add <4 x i32> %wide.load32, %vec.phi21
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%35 = add <4 x i32> zeroinitializer, %vec.phi23
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%36 = add <4 x i32> zeroinitializer, %vec.phi24
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%37 = add <4 x i32> %wide.load36, %vec.phi25
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%38 = add <4 x i32> %wide.load37, %vec.phi26
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%39 = add <4 x i32> %wide.load38, %vec.phi27
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%40 = add <4 x i32> %wide.load39, %vec.phi28
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%41 = add <4 x i32> %wide.load40, %vec.phi29
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%42 = add <4 x i32> %wide.load41, %vec.phi30
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%43 = sub <4 x i32> %32, %wide.load42
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%44 = sub <4 x i32> %33, %wide.load43
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%45 = sub <4 x i32> %34, %wide.load44
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%46 = sub <4 x i32> %35, %wide.load46
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%47 = sub <4 x i32> %36, %wide.load47
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%48 = sub <4 x i32> %37, %wide.load48
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%49 = sub <4 x i32> %38, %wide.load49
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%50 = sub <4 x i32> %39, %wide.load50
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%51 = sub <4 x i32> %40, %wide.load51
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%52 = sub <4 x i32> %41, %wide.load52
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%53 = sub <4 x i32> %42, %wide.load53
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%index.next = add i64 %index, 48
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br i1 false, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body
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%.lcssa112 = phi <4 x i32> [ %53, %vector.body ]
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%.lcssa111 = phi <4 x i32> [ %52, %vector.body ]
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%.lcssa110 = phi <4 x i32> [ %51, %vector.body ]
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%.lcssa109 = phi <4 x i32> [ %50, %vector.body ]
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%.lcssa108 = phi <4 x i32> [ %49, %vector.body ]
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%.lcssa107 = phi <4 x i32> [ %48, %vector.body ]
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%.lcssa106 = phi <4 x i32> [ %47, %vector.body ]
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%.lcssa105 = phi <4 x i32> [ %46, %vector.body ]
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%.lcssa103 = phi <4 x i32> [ %45, %vector.body ]
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%.lcssa102 = phi <4 x i32> [ %44, %vector.body ]
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%.lcssa = phi <4 x i32> [ %43, %vector.body ]
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ret void
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}
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attributes #0 = { noinline nounwind }
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@ -0,0 +1,115 @@
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; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind
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define void @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc(i32* nocapture readonly %first) #0 {
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entry:
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br i1 false, label %loop2_start, label %if.end5
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; CHECK-LABEL: @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc
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; CHECK: xxlor
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loop2_start: ; preds = %loop2_start, %entry
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br i1 undef, label %loop2_start, label %if.then.i31
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if.end5: ; preds = %entry
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br i1 undef, label %loop_start.preheader, label %if.then.i31
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loop_start.preheader: ; preds = %if.end5
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br i1 false, label %middle.block, label %vector.body
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vector.body: ; preds = %vector.body, %loop_start.preheader
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%vec.phi61 = phi <4 x i32> [ %34, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi62 = phi <4 x i32> [ %35, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi63 = phi <4 x i32> [ %36, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi65 = phi <4 x i32> [ %37, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi67 = phi <4 x i32> [ %38, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi68 = phi <4 x i32> [ %39, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi69 = phi <4 x i32> [ %40, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi70 = phi <4 x i32> [ %41, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%vec.phi71 = phi <4 x i32> [ %42, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
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%.sum = add i64 0, 4
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%wide.load72 = load <4 x i32>* null, align 4
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%.sum109 = add i64 0, 8
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%0 = getelementptr i32* %first, i64 %.sum109
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%1 = bitcast i32* %0 to <4 x i32>*
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%wide.load73 = load <4 x i32>* %1, align 4
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%.sum110 = add i64 0, 12
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%2 = getelementptr i32* %first, i64 %.sum110
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%3 = bitcast i32* %2 to <4 x i32>*
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%wide.load74 = load <4 x i32>* %3, align 4
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%.sum112 = add i64 0, 20
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%4 = getelementptr i32* %first, i64 %.sum112
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%5 = bitcast i32* %4 to <4 x i32>*
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%wide.load76 = load <4 x i32>* %5, align 4
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%.sum114 = add i64 0, 28
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%6 = getelementptr i32* %first, i64 %.sum114
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%7 = bitcast i32* %6 to <4 x i32>*
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%wide.load78 = load <4 x i32>* %7, align 4
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%.sum115 = add i64 0, 32
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%8 = getelementptr i32* %first, i64 %.sum115
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%9 = bitcast i32* %8 to <4 x i32>*
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%wide.load79 = load <4 x i32>* %9, align 4
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%.sum116 = add i64 0, 36
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%10 = getelementptr i32* %first, i64 %.sum116
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%11 = bitcast i32* %10 to <4 x i32>*
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%wide.load80 = load <4 x i32>* %11, align 4
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%.sum117 = add i64 0, 40
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%12 = getelementptr i32* %first, i64 %.sum117
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%13 = bitcast i32* %12 to <4 x i32>*
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%wide.load81 = load <4 x i32>* %13, align 4
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%.sum118 = add i64 0, 44
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%14 = getelementptr i32* %first, i64 %.sum118
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%15 = bitcast i32* %14 to <4 x i32>*
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%wide.load82 = load <4 x i32>* %15, align 4
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%16 = mul <4 x i32> %wide.load72, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%17 = mul <4 x i32> %wide.load73, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%18 = mul <4 x i32> %wide.load74, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%19 = mul <4 x i32> %wide.load76, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%20 = mul <4 x i32> %wide.load78, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%21 = mul <4 x i32> %wide.load79, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%22 = mul <4 x i32> %wide.load80, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%23 = mul <4 x i32> %wide.load81, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%24 = mul <4 x i32> %wide.load82, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
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%25 = add <4 x i32> %16, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%26 = add <4 x i32> %17, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%27 = add <4 x i32> %18, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%28 = add <4 x i32> %19, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%29 = add <4 x i32> %20, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%30 = add <4 x i32> %21, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%31 = add <4 x i32> %22, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%32 = add <4 x i32> %23, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%33 = add <4 x i32> %24, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
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%34 = add nsw <4 x i32> %25, %vec.phi61
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%35 = add nsw <4 x i32> %26, %vec.phi62
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%36 = add nsw <4 x i32> %27, %vec.phi63
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%37 = add nsw <4 x i32> %28, %vec.phi65
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%38 = add nsw <4 x i32> %29, %vec.phi67
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%39 = add nsw <4 x i32> %30, %vec.phi68
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%40 = add nsw <4 x i32> %31, %vec.phi69
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%41 = add nsw <4 x i32> %32, %vec.phi70
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%42 = add nsw <4 x i32> %33, %vec.phi71
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br i1 false, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body, %loop_start.preheader
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%rdx.vec.exit.phi85 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %34, %vector.body ]
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%rdx.vec.exit.phi86 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %35, %vector.body ]
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%rdx.vec.exit.phi87 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %36, %vector.body ]
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%rdx.vec.exit.phi89 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %37, %vector.body ]
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%rdx.vec.exit.phi91 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %38, %vector.body ]
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%rdx.vec.exit.phi92 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %39, %vector.body ]
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%rdx.vec.exit.phi93 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %40, %vector.body ]
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%rdx.vec.exit.phi94 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %41, %vector.body ]
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%rdx.vec.exit.phi95 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %42, %vector.body ]
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br i1 false, label %if.then.i31, label %loop_start.prol
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||||
|
||||
loop_start.prol: ; preds = %loop_start.prol, %middle.block
|
||||
br label %loop_start.prol
|
||||
|
||||
if.then.i31: ; preds = %middle.block, %if.end5, %loop2_start
|
||||
unreachable
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
|
||||
Loading…
Reference in New Issue