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[X86] X86SpeculativeLoadHardening.cpp - pass DebugLoc by const reference not value.

This commit is contained in:
Simon Pilgrim 2022-06-07 12:38:05 +01:00
parent 1b6d3bdc82
commit 5cea1553b8
1 changed files with 14 additions and 13 deletions
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27
llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
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@ -181,17 +181,18 @@ private:
void tracePredStateThroughBlocksAndHarden(MachineFunction &MF); void tracePredStateThroughBlocksAndHarden(MachineFunction &MF);
unsigned saveEFLAGS(MachineBasicBlock &MBB, unsigned saveEFLAGS(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertPt, DebugLoc Loc); MachineBasicBlock::iterator InsertPt,
const DebugLoc &Loc);
void restoreEFLAGS(MachineBasicBlock &MBB, void restoreEFLAGS(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertPt, DebugLoc Loc, MachineBasicBlock::iterator InsertPt, const DebugLoc &Loc,
Register Reg); Register Reg);
void mergePredStateIntoSP(MachineBasicBlock &MBB, void mergePredStateIntoSP(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertPt, DebugLoc Loc, MachineBasicBlock::iterator InsertPt,
unsigned PredStateReg); const DebugLoc &Loc, unsigned PredStateReg);
unsigned extractPredStateFromSP(MachineBasicBlock &MBB, unsigned extractPredStateFromSP(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertPt, MachineBasicBlock::iterator InsertPt,
DebugLoc Loc); const DebugLoc &Loc);
void void
hardenLoadAddr(MachineInstr &MI, MachineOperand &BaseMO, hardenLoadAddr(MachineInstr &MI, MachineOperand &BaseMO,
@ -203,7 +204,7 @@ private:
bool canHardenRegister(Register Reg); bool canHardenRegister(Register Reg);
unsigned hardenValueInRegister(Register Reg, MachineBasicBlock &MBB, unsigned hardenValueInRegister(Register Reg, MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertPt, MachineBasicBlock::iterator InsertPt,
DebugLoc Loc); const DebugLoc &Loc);
unsigned hardenPostLoad(MachineInstr &MI); unsigned hardenPostLoad(MachineInstr &MI);
void hardenReturnInstr(MachineInstr &MI); void hardenReturnInstr(MachineInstr &MI);
void tracePredStateThroughCall(MachineInstr &MI); void tracePredStateThroughCall(MachineInstr &MI);
@ -1500,7 +1501,7 @@ void X86SpeculativeLoadHardeningPass::tracePredStateThroughBlocksAndHarden(
/// as the save so that no PHI nodes are inserted. /// as the save so that no PHI nodes are inserted.
unsigned X86SpeculativeLoadHardeningPass::saveEFLAGS( unsigned X86SpeculativeLoadHardeningPass::saveEFLAGS(
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt,
DebugLoc Loc) { const DebugLoc &Loc) {
// FIXME: Hard coding this to a 32-bit register class seems weird, but matches // FIXME: Hard coding this to a 32-bit register class seems weird, but matches
// what instruction selection does. // what instruction selection does.
Register Reg = MRI->createVirtualRegister(&X86::GR32RegClass); Register Reg = MRI->createVirtualRegister(&X86::GR32RegClass);
@ -1517,8 +1518,8 @@ unsigned X86SpeculativeLoadHardeningPass::saveEFLAGS(
/// This must be done within the same basic block as the save in order to /// This must be done within the same basic block as the save in order to
/// reliably lower. /// reliably lower.
void X86SpeculativeLoadHardeningPass::restoreEFLAGS( void X86SpeculativeLoadHardeningPass::restoreEFLAGS(
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, DebugLoc Loc, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt,
Register Reg) { const DebugLoc &Loc, Register Reg) {
BuildMI(MBB, InsertPt, Loc, TII->get(X86::COPY), X86::EFLAGS).addReg(Reg); BuildMI(MBB, InsertPt, Loc, TII->get(X86::COPY), X86::EFLAGS).addReg(Reg);
++NumInstsInserted; ++NumInstsInserted;
} }
@ -1528,8 +1529,8 @@ void X86SpeculativeLoadHardeningPass::restoreEFLAGS(
/// a way that won't form non-canonical pointers and also will be preserved /// a way that won't form non-canonical pointers and also will be preserved
/// across normal stack adjustments. /// across normal stack adjustments.
void X86SpeculativeLoadHardeningPass::mergePredStateIntoSP( void X86SpeculativeLoadHardeningPass::mergePredStateIntoSP(
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, DebugLoc Loc, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt,
unsigned PredStateReg) { const DebugLoc &Loc, unsigned PredStateReg) {
Register TmpReg = MRI->createVirtualRegister(PS->RC); Register TmpReg = MRI->createVirtualRegister(PS->RC);
// FIXME: This hard codes a shift distance based on the number of bits needed // FIXME: This hard codes a shift distance based on the number of bits needed
// to stay canonical on 64-bit. We should compute this somehow and support // to stay canonical on 64-bit. We should compute this somehow and support
@ -1549,7 +1550,7 @@ void X86SpeculativeLoadHardeningPass::mergePredStateIntoSP(
/// Extracts the predicate state stored in the high bits of the stack pointer. /// Extracts the predicate state stored in the high bits of the stack pointer.
unsigned X86SpeculativeLoadHardeningPass::extractPredStateFromSP( unsigned X86SpeculativeLoadHardeningPass::extractPredStateFromSP(
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt,
DebugLoc Loc) { const DebugLoc &Loc) {
Register PredStateReg = MRI->createVirtualRegister(PS->RC); Register PredStateReg = MRI->createVirtualRegister(PS->RC);
Register TmpReg = MRI->createVirtualRegister(PS->RC); Register TmpReg = MRI->createVirtualRegister(PS->RC);
@ -1907,7 +1908,7 @@ bool X86SpeculativeLoadHardeningPass::canHardenRegister(Register Reg) {
/// register class as `Reg`. /// register class as `Reg`.
unsigned X86SpeculativeLoadHardeningPass::hardenValueInRegister( unsigned X86SpeculativeLoadHardeningPass::hardenValueInRegister(
Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt,
DebugLoc Loc) { const DebugLoc &Loc) {
assert(canHardenRegister(Reg) && "Cannot harden this register!"); assert(canHardenRegister(Reg) && "Cannot harden this register!");
assert(Reg.isVirtual() && "Cannot harden a physical register!"); assert(Reg.isVirtual() && "Cannot harden a physical register!");