forked from OSchip/llvm-project
[AMDGPU] Add all vgpr classes to asm parser
Differential Revision: https://reviews.llvm.org/D65158 llvm-svn: 366917
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@ -275,8 +275,10 @@ public:
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isRegClass(AMDGPU::VReg_64RegClassID) ||
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isRegClass(AMDGPU::VReg_96RegClassID) ||
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isRegClass(AMDGPU::VReg_128RegClassID) ||
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isRegClass(AMDGPU::VReg_160RegClassID) ||
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isRegClass(AMDGPU::VReg_256RegClassID) ||
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isRegClass(AMDGPU::VReg_512RegClassID);
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isRegClass(AMDGPU::VReg_512RegClassID) ||
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isRegClass(AMDGPU::VReg_1024RegClassID);
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}
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bool isVReg32() const {
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@ -1872,8 +1874,10 @@ static int getRegClass(RegisterKind Is, unsigned RegWidth) {
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case 2: return AMDGPU::VReg_64RegClassID;
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case 3: return AMDGPU::VReg_96RegClassID;
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case 4: return AMDGPU::VReg_128RegClassID;
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case 5: return AMDGPU::VReg_160RegClassID;
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case 8: return AMDGPU::VReg_256RegClassID;
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case 16: return AMDGPU::VReg_512RegClassID;
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case 32: return AMDGPU::VReg_1024RegClassID;
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}
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} else if (Is == IS_TTMP) {
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switch (RegWidth) {
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@ -5977,6 +5977,9 @@ image_load v5, v[1:4], s[8:15] dmask:0x1 da
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image_load v5, v[1:4], s[8:15] dmask:0x1 d16
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// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x80]
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image_load v[0:4], v5, s[0:7] dmask:0xf unorm tfe
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// CHECK: [0x00,0x1f,0x01,0xf0,0x05,0x00,0x00,0x00]
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image_load_mip v5, v[1:4], s[8:15] dmask:0x1
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// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
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@ -32,10 +32,10 @@ v_accvgpr_write_b32 a0, v0
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// GFX900: error: instruction not supported on this GPU
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v_mfma_f32_32x32x1f32 v[0:31], v0, v1, a[1:32]
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// GFX908: error: not a valid operand
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// GFX908: error: invalid operand for instruction
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v_mfma_f32_32x32x1f32 a[0:31], v0, v1, v[1:32]
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// GFX908: error: not a valid operand
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// GFX908: error: invalid operand for instruction
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v_mfma_f32_32x32x1f32 a[0:31], s0, v1, a[1:32]
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// GFX908: error: invalid operand for instruction
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