forked from OSchip/llvm-project
AMDGPU: Serialize WWM registers
This commit is contained in:
Matt Arsenault
parent
9592e88f59
commit
5cd17f9d43
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@ -1449,6 +1449,14 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
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return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
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}
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for (const auto &YamlReg : YamlMFI.WWMReservedRegs) {
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Register ParsedReg;
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if (parseRegister(YamlReg, ParsedReg))
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return true;
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MFI->reserveWWMRegister(ParsedReg);
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}
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auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
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const TargetRegisterClass &RC,
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ArgDescriptor &Arg, unsigned UserSGPRs,
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@ -589,6 +589,9 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
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FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
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StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
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ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
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for (Register Reg : MFI.WWMReservedRegs)
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WWMReservedRegs.push_back(regToString(Reg, TRI));
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auto SFI = MFI.getOptionalScavengeFI();
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if (SFI)
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ScavengeFI = yaml::FrameIndex(*SFI, MF.getFrameInfo());
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@ -283,6 +283,8 @@ struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
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// TODO: 10 may be a better default since it's the maximum.
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unsigned Occupancy = 0;
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SmallVector<StringValue> WWMReservedRegs;
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StringValue ScratchRSrcReg = "$private_rsrc_reg";
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StringValue FrameOffsetReg = "$fp_reg";
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StringValue StackPtrOffsetReg = "$sp_reg";
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@ -324,6 +326,7 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
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YamlIO.mapOptional("highBitsOf32BitAddress",
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MFI.HighBitsOf32BitAddress, 0u);
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YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
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YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
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YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
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}
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};
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@ -1,4 +1,4 @@
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=si-pre-allocate-wwm-regs -o %t.mir %s
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; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s
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; Test that SIMachineFunctionInfo can be round trip serialized through
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@ -200,8 +200,25 @@ define amdgpu_ps void @high_address_bits() #4 {
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ret void
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}
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; CHECK-LABEL: {{^}}name: wwm_reserved_regs
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; CHECK: wwmReservedRegs:
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; CHECK-NEXT: - '$vgpr2'
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; CHECK-NEXT: - '$vgpr3'
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define amdgpu_cs void @wwm_reserved_regs(i32 addrspace(1)* %ptr, <4 x i32> inreg %tmp14) {
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%ld0 = load volatile i32, i32 addrspace(1)* %ptr
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%ld1 = load volatile i32, i32 addrspace(1)* %ptr
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%inactive0 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %ld1, i32 0)
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%inactive1 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %ld0, i32 0)
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store volatile i32 %inactive0, i32 addrspace(1)* %ptr
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store volatile i32 %inactive1, i32 addrspace(1)* %ptr
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ret void
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}
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declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #5
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attributes #0 = { "no-signed-zeros-fp-math" = "true" }
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attributes #1 = { "amdgpu-dx10-clamp" = "false" }
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attributes #2 = { "amdgpu-ieee" = "false" }
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attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" }
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attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" }
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attributes #5 = { convergent nounwind readnone willreturn }
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@ -0,0 +1,12 @@
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# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
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---
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name: invalid_reg
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machineFunctionInfo:
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# ERR: [[@LINE+1]]:32: unknown register name 'notareg'
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wwmReservedRegs: ['$vgpr0', '$notareg']
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body: |
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bb.0:
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S_ENDPGM 0
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...
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@ -0,0 +1,12 @@
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# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
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---
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name: invalid_reg
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machineFunctionInfo:
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# ERR: [[@LINE+1]]:21: expected a named register
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wwmReservedRegs: [123]
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body: |
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bb.0:
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S_ENDPGM 0
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...
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@ -0,0 +1,44 @@
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
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# CHECK-LABEL: name: empty_wwm_regs{{$}}
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# CHECK: machineFunctionInfo:
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# CHECK-NOT: wwmReservedRegs
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---
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name: empty_wwm_regs
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machineFunctionInfo:
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wwmReservedRegs: []
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body: |
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bb.0:
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S_ENDPGM 0
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...
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# CHECK-LABEL: name: one_reg{{$}}
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# CHECK: machineFunctionInfo:
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# CHECK: wwmReservedRegs:
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# CHECK-NEXT: - '$vgpr0'
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---
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name: one_reg
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machineFunctionInfo:
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wwmReservedRegs: ['$vgpr0']
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body: |
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bb.0:
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S_ENDPGM 0
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...
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# CHECK-LABEL: name: two_reg{{$}}
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# CHECK: machineFunctionInfo:
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# CHECK: wwmReservedRegs:
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# CHECK-NEXT: - '$vgpr0'
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# CHECK-NEXT: - '$vgpr1'
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---
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name: two_reg
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machineFunctionInfo:
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wwmReservedRegs: ['$vgpr0', '$vgpr1']
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body: |
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bb.0:
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S_ENDPGM 0
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...
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