forked from OSchip/llvm-project
[X86] Make the multiply and divide itineraries more consistent.
Sometimes we used the same itinerary for MEM and REG forms, but that seems inconsistent with our usual usage. We also used the MUL8 itinerary for MULX32/64 which was also weird. The test changes are because we were using IIC_IMUL32_RR and IIC_IMUL64_RR instead of IIC_IMUL32_REG/IIC_IMUL64_REG for the 32 and 64 bit multiplies that produce double width result. llvm-svn: 327866
This commit is contained in:
Craig Topper
parent
a6137e2b23
commit
5ccd87233f
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@ -63,7 +63,7 @@ def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
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// This probably ought to be moved to a def : Pat<> if the
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// syntax can be accepted.
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[(set AL, (mul AL, GR8:$src)),
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(implicit EFLAGS)], IIC_MUL8>, Sched<[WriteIMul]>;
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(implicit EFLAGS)], IIC_MUL8_REG>, Sched<[WriteIMul]>;
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// AX,DX = AX*GR16
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let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
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def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
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@ -80,7 +80,7 @@ let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
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def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
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"mul{q}\t$src",
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[/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
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IIC_MUL64>, Sched<[WriteIMul]>;
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IIC_MUL64_REG>, Sched<[WriteIMul]>;
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// AL,AH = AL*[mem8]
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let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
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@ -89,7 +89,7 @@ def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
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// This probably ought to be moved to a def : Pat<> if the
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// syntax can be accepted.
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[(set AL, (mul AL, (loadi8 addr:$src))),
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(implicit EFLAGS)], IIC_MUL8>, SchedLoadReg<WriteIMulLd>;
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(implicit EFLAGS)], IIC_MUL8_MEM>, SchedLoadReg<WriteIMulLd>;
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// AX,DX = AX*[mem16]
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let mayLoad = 1, hasSideEffects = 0 in {
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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@ -104,7 +104,7 @@ def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
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// RAX,RDX = RAX*[mem64]
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
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"mul{q}\t$src", [], IIC_MUL64>, SchedLoadReg<WriteIMulLd>,
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"mul{q}\t$src", [], IIC_MUL64_MEM>, SchedLoadReg<WriteIMulLd>,
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Requires<[In64BitMode]>;
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}
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@ -112,25 +112,25 @@ let hasSideEffects = 0 in {
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// AL,AH = AL*GR8
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let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [],
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IIC_IMUL8>, Sched<[WriteIMul]>;
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IIC_IMUL8_REG>, Sched<[WriteIMul]>;
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// AX,DX = AX*GR16
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],
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IIC_IMUL16_RR>, OpSize16, Sched<[WriteIMul]>;
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IIC_IMUL16_REG>, OpSize16, Sched<[WriteIMul]>;
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// EAX,EDX = EAX*GR32
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
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IIC_IMUL32_RR>, OpSize32, Sched<[WriteIMul]>;
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IIC_IMUL32_REG>, OpSize32, Sched<[WriteIMul]>;
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// RAX,RDX = RAX*GR64
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
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IIC_IMUL64_RR>, Sched<[WriteIMul]>;
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IIC_IMUL64_REG>, Sched<[WriteIMul]>;
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let mayLoad = 1 in {
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// AL,AH = AL*[mem8]
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let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
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"imul{b}\t$src", [], IIC_IMUL8>, SchedLoadReg<WriteIMulLd>;
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"imul{b}\t$src", [], IIC_IMUL8_MEM>, SchedLoadReg<WriteIMulLd>;
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// AX,DX = AX*[mem16]
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
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@ -144,7 +144,7 @@ def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
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// RAX,RDX = RAX*[mem64]
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
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"imul{q}\t$src", [], IIC_IMUL64>, SchedLoadReg<WriteIMulLd>,
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"imul{q}\t$src", [], IIC_IMUL64_MEM>, SchedLoadReg<WriteIMulLd>,
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Requires<[In64BitMode]>;
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}
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} // hasSideEffects
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@ -301,14 +301,14 @@ def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
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"div{b}\t$src", [], IIC_DIV8_REG>;
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let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
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def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
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"div{w}\t$src", [], IIC_DIV16>, OpSize16;
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"div{w}\t$src", [], IIC_DIV16_REG>, OpSize16;
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
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def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
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"div{l}\t$src", [], IIC_DIV32>, OpSize32;
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"div{l}\t$src", [], IIC_DIV32_REG>, OpSize32;
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// RDX:RAX/r64 = RAX,RDX
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
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def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
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"div{q}\t$src", [], IIC_DIV64>;
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"div{q}\t$src", [], IIC_DIV64_REG>;
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} // SchedRW
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let mayLoad = 1 in {
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@ -318,16 +318,16 @@ def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
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SchedLoadReg<WriteIDivLd>;
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let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
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def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
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"div{w}\t$src", [], IIC_DIV16>, OpSize16,
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"div{w}\t$src", [], IIC_DIV16_MEM>, OpSize16,
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SchedLoadReg<WriteIDivLd>;
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
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def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
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"div{l}\t$src", [], IIC_DIV32>,
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"div{l}\t$src", [], IIC_DIV32_MEM>,
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SchedLoadReg<WriteIDivLd>, OpSize32;
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// RDX:RAX/[mem64] = RAX,RDX
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
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def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
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"div{q}\t$src", [], IIC_DIV64>,
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"div{q}\t$src", [], IIC_DIV64_MEM>,
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SchedLoadReg<WriteIDivLd>, Requires<[In64BitMode]>;
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}
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@ -335,35 +335,35 @@ def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
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let SchedRW = [WriteIDiv] in {
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let Defs = [AL,AH,EFLAGS], Uses = [AX] in
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def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
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"idiv{b}\t$src", [], IIC_IDIV8>;
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"idiv{b}\t$src", [], IIC_IDIV8_REG>;
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let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
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def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
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"idiv{w}\t$src", [], IIC_IDIV16>, OpSize16;
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"idiv{w}\t$src", [], IIC_IDIV16_REG>, OpSize16;
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
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def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
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"idiv{l}\t$src", [], IIC_IDIV32>, OpSize32;
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"idiv{l}\t$src", [], IIC_IDIV32_REG>, OpSize32;
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// RDX:RAX/r64 = RAX,RDX
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
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def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
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"idiv{q}\t$src", [], IIC_IDIV64>;
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"idiv{q}\t$src", [], IIC_IDIV64_REG>;
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} // SchedRW
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let mayLoad = 1 in {
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let Defs = [AL,AH,EFLAGS], Uses = [AX] in
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def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
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"idiv{b}\t$src", [], IIC_IDIV8>,
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"idiv{b}\t$src", [], IIC_IDIV8_MEM>,
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SchedLoadReg<WriteIDivLd>;
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let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
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def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
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"idiv{w}\t$src", [], IIC_IDIV16>, OpSize16,
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"idiv{w}\t$src", [], IIC_IDIV16_MEM>, OpSize16,
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SchedLoadReg<WriteIDivLd>;
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
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def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
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"idiv{l}\t$src", [], IIC_IDIV32>, OpSize32,
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"idiv{l}\t$src", [], IIC_IDIV32_MEM>, OpSize32,
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SchedLoadReg<WriteIDivLd>;
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
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def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
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"idiv{q}\t$src", [], IIC_IDIV64>,
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"idiv{q}\t$src", [], IIC_IDIV64_MEM>,
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SchedLoadReg<WriteIDivLd>, Requires<[In64BitMode]>;
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}
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} // hasSideEffects = 0
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@ -1306,25 +1306,28 @@ let Predicates = [HasBMI], AddedComplexity = -6 in {
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//===----------------------------------------------------------------------===//
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// MULX Instruction
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//
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multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop> {
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multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop,
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InstrItinClass itin_reg, InstrItinClass itin_mem> {
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let hasSideEffects = 0 in {
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let isCommutable = 1 in
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def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
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!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
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[], IIC_MUL8>, T8XD, VEX_4V, Sched<[WriteIMul, WriteIMulH]>;
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[], itin_reg>, T8XD, VEX_4V, Sched<[WriteIMul, WriteIMulH]>;
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let mayLoad = 1 in
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def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
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!strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
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[], IIC_MUL8>, T8XD, VEX_4V, Sched<[WriteIMulLd, WriteIMulH]>;
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[], itin_mem>, T8XD, VEX_4V, Sched<[WriteIMulLd, WriteIMulH]>;
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}
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}
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let Predicates = [HasBMI2] in {
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let Uses = [EDX] in
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defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem>;
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defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, IIC_MUL32_REG,
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IIC_MUL32_MEM>;
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let Uses = [RDX] in
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defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem>, VEX_W;
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defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, IIC_MUL64_REG,
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IIC_MUL64_MEM>, VEX_W;
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}
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//===----------------------------------------------------------------------===//
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@ -146,19 +146,23 @@ def IIC_ALU_MEM : InstrItinClass;
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def IIC_ALU_NONMEM : InstrItinClass;
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def IIC_LEA : InstrItinClass;
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def IIC_LEA_16 : InstrItinClass;
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def IIC_MUL8 : InstrItinClass;
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def IIC_MUL8_MEM : InstrItinClass;
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def IIC_MUL8_REG : InstrItinClass;
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def IIC_MUL16_MEM : InstrItinClass;
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def IIC_MUL16_REG : InstrItinClass;
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def IIC_MUL32_MEM : InstrItinClass;
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def IIC_MUL32_REG : InstrItinClass;
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def IIC_MUL64 : InstrItinClass;
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def IIC_MUL64_MEM : InstrItinClass;
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def IIC_MUL64_REG : InstrItinClass;
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// imul by al, ax, eax, tax
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def IIC_IMUL8 : InstrItinClass;
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def IIC_IMUL8_MEM : InstrItinClass;
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def IIC_IMUL8_REG : InstrItinClass;
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def IIC_IMUL16_MEM : InstrItinClass;
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def IIC_IMUL16_REG : InstrItinClass;
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def IIC_IMUL32_MEM : InstrItinClass;
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def IIC_IMUL32_REG : InstrItinClass;
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def IIC_IMUL64 : InstrItinClass;
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def IIC_IMUL64_MEM : InstrItinClass;
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def IIC_IMUL64_REG : InstrItinClass;
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// imul reg by reg|mem
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def IIC_IMUL16_RM : InstrItinClass;
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def IIC_IMUL16_RR : InstrItinClass;
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@ -176,14 +180,21 @@ def IIC_IMUL64_RRI : InstrItinClass;
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// div
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def IIC_DIV8_MEM : InstrItinClass;
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def IIC_DIV8_REG : InstrItinClass;
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def IIC_DIV16 : InstrItinClass;
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def IIC_DIV32 : InstrItinClass;
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def IIC_DIV64 : InstrItinClass;
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def IIC_DIV16_MEM : InstrItinClass;
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def IIC_DIV16_REG : InstrItinClass;
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def IIC_DIV32_MEM : InstrItinClass;
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def IIC_DIV32_REG : InstrItinClass;
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def IIC_DIV64_MEM : InstrItinClass;
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def IIC_DIV64_REG : InstrItinClass;
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// idiv
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def IIC_IDIV8 : InstrItinClass;
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def IIC_IDIV16 : InstrItinClass;
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def IIC_IDIV32 : InstrItinClass;
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def IIC_IDIV64 : InstrItinClass;
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def IIC_IDIV8_MEM : InstrItinClass;
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def IIC_IDIV8_REG : InstrItinClass;
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def IIC_IDIV16_MEM : InstrItinClass;
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def IIC_IDIV16_REG : InstrItinClass;
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def IIC_IDIV32_MEM : InstrItinClass;
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def IIC_IDIV32_REG : InstrItinClass;
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def IIC_IDIV64_MEM : InstrItinClass;
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def IIC_IDIV64_REG : InstrItinClass;
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// neg/not/inc/dec
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def IIC_UNARY_REG : InstrItinClass;
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def IIC_UNARY_MEM : InstrItinClass;
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@ -38,19 +38,23 @@ def AtomItineraries : ProcessorItineraries<
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InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
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InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >,
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// mul
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InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL8_MEM, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL8_REG, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL64, [InstrStage<12, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL64_MEM, [InstrStage<12, [Port0, Port1]>] >,
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InstrItinData<IIC_MUL64_REG, [InstrStage<12, [Port0, Port1]>] >,
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// imul by al, ax, eax, rax
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InstrItinData<IIC_IMUL8, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL8_MEM, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL8_REG, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL16_MEM, [InstrStage<8, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL16_REG, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL32_MEM, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL32_REG, [InstrStage<6, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL64, [InstrStage<12, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL64_MEM, [InstrStage<12, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL64_REG, [InstrStage<12, [Port0, Port1]>] >,
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// imul reg by reg|mem
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InstrItinData<IIC_IMUL16_RM, [InstrStage<7, [Port0, Port1]>] >,
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InstrItinData<IIC_IMUL16_RR, [InstrStage<6, [Port0, Port1]>] >,
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@ -66,16 +70,23 @@ def AtomItineraries : ProcessorItineraries<
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InstrItinData<IIC_IMUL32_RMI, [InstrStage<5, [Port0]>] >,
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InstrItinData<IIC_IMUL64_RMI, [InstrStage<14, [Port0, Port1]>] >,
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// idiv
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InstrItinData<IIC_IDIV8, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV16, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV32, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV64, [InstrStage<130, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV8_MEM, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV8_REG, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV16_MEM, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV16_REG, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV32_MEM, [InstrStage<62, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV32_REG, [InstrStage<62, [Port0, Port1]>] >,
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||||
InstrItinData<IIC_IDIV64_MEM, [InstrStage<130, [Port0, Port1]>] >,
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InstrItinData<IIC_IDIV64_REG, [InstrStage<130, [Port0, Port1]>] >,
|
||||
// div
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InstrItinData<IIC_DIV8_REG, [InstrStage<50, [Port0, Port1]>] >,
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InstrItinData<IIC_DIV8_MEM, [InstrStage<68, [Port0, Port1]>] >,
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InstrItinData<IIC_DIV16, [InstrStage<50, [Port0, Port1]>] >,
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InstrItinData<IIC_DIV32, [InstrStage<50, [Port0, Port1]>] >,
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InstrItinData<IIC_DIV64, [InstrStage<130, [Port0, Port1]>] >,
|
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InstrItinData<IIC_DIV16_MEM, [InstrStage<50, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_DIV16_REG, [InstrStage<50, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_DIV32_MEM, [InstrStage<50, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_DIV32_REG, [InstrStage<50, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_DIV64_MEM, [InstrStage<130, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_DIV64_REG, [InstrStage<130, [Port0, Port1]>] >,
|
||||
// neg/not/inc/dec
|
||||
InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_UNARY_MEM, [InstrStage<1, [Port0]>] >,
|
||||
|
|
|
|||
|
|
@ -5640,7 +5640,7 @@ define void @test_imul_16(i16 %a0, i16* %a1) optsize {
|
|||
; ATOM-LABEL: test_imul_16:
|
||||
; ATOM: # %bb.0:
|
||||
; ATOM-NEXT: #APP
|
||||
; ATOM-NEXT: imulw %di # sched: [6:3.00]
|
||||
; ATOM-NEXT: imulw %di # sched: [7:3.50]
|
||||
; ATOM-NEXT: imulw (%rsi) # sched: [8:4.00]
|
||||
; ATOM-NEXT: imulw %di, %di # sched: [6:3.00]
|
||||
; ATOM-NEXT: imulw (%rsi), %di # sched: [7:3.50]
|
||||
|
|
@ -5803,7 +5803,7 @@ define void @test_imul_32(i32 %a0, i32* %a1) optsize {
|
|||
; ATOM-LABEL: test_imul_32:
|
||||
; ATOM: # %bb.0:
|
||||
; ATOM-NEXT: #APP
|
||||
; ATOM-NEXT: imull %edi # sched: [5:5.00]
|
||||
; ATOM-NEXT: imull %edi # sched: [6:3.00]
|
||||
; ATOM-NEXT: imull (%rsi) # sched: [7:3.50]
|
||||
; ATOM-NEXT: imull %edi, %edi # sched: [5:5.00]
|
||||
; ATOM-NEXT: imull (%rsi), %edi # sched: [5:5.00]
|
||||
|
|
|
|||
Loading…
Reference in New Issue