forked from OSchip/llvm-project
[AVR] Use the register scavenger when expanding 'LDDW' instructions
Summary: This gets rid of the hardcoded 'r0' that was used previously. Reviewers: asl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27567 llvm-svn: 289322
This commit is contained in:
Dylan McKay
parent
5d0233bea2
commit
5c90b8cb4f
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@ -21,6 +21,7 @@
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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@ -110,6 +111,9 @@ bool AVRExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TRI = STI.getRegisterInfo();
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TII = STI.getInstrInfo();
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// We need to track liveness in order to use register scavenging.
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MF.getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
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for (Block &MBB : MF) {
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bool ContinueExpanding = true;
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unsigned ExpandCount = 0;
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@ -656,8 +660,7 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
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assert(Imm <= 63 && "Offset is out of range");
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unsigned TmpLoReg = DstLoReg;
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unsigned TmpHiReg = DstHiReg;
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MachineInstr *MIBLO, *MIBHI;
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// HACK: We shouldn't have instances of this instruction
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// where src==dest because the instruction itself is
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@ -666,34 +669,51 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
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//
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// In this case, just use a temporary register.
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if (DstReg == SrcReg) {
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TmpLoReg = SCRATCH_REGISTER;
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TmpHiReg = SCRATCH_REGISTER;
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RegScavenger RS;
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RS.enterBasicBlock(MBB);
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RS.forward(MBBI);
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BitVector Candidates =
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TRI->getAllocatableSet
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(*MBB.getParent(), &AVR::GPR8RegClass);
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// Exclude all the registers being used by the instruction.
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for (MachineOperand &MO : MI.operands()) {
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if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
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!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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Candidates.reset(MO.getReg());
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}
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auto MIBLO = buildMI(MBB, MBBI, OpLo)
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.addReg(TmpLoReg, RegState::Define | getDeadRegState(DstIsDead))
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BitVector Available = RS.getRegsAvailable(&AVR::GPR8RegClass);
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Available &= Candidates;
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unsigned TmpReg = Available.find_first();
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assert(TmpReg != -1 && "ran out of registers");
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MIBLO = buildMI(MBB, MBBI, OpLo)
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.addReg(TmpReg, RegState::Define)
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.addReg(SrcReg)
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.addImm(Imm);
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// Push the low part of the temporary register to the stack.
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if (TmpLoReg != DstLoReg)
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buildMI(MBB, MBBI, AVR::PUSHRr)
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.addReg(AVR::R0);
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buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstLoReg).addReg(TmpReg);
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auto MIBHI = buildMI(MBB, MBBI, OpHi)
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.addReg(TmpHiReg, RegState::Define | getDeadRegState(DstIsDead))
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MIBHI = buildMI(MBB, MBBI, OpHi)
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.addReg(TmpReg, RegState::Define)
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.addReg(SrcReg, getKillRegState(SrcIsKill))
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.addImm(Imm + 1);
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// If we need to use a temporary register.
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if (TmpHiReg != DstHiReg) {
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// Move the hi result from the tmp register to the destination.
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buildMI(MBB, MBBI, AVR::MOVRdRr)
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.addReg(DstHiReg).addReg(SCRATCH_REGISTER);
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buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
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} else {
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MIBLO = buildMI(MBB, MBBI, OpLo)
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.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(SrcReg)
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.addImm(Imm);
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// Pop the lo result calculated previously and put it into
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// the lo destination.
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buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
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MIBHI = buildMI(MBB, MBBI, OpHi)
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.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(SrcReg, getKillRegState(SrcIsKill))
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.addImm(Imm + 1);
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}
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MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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@ -1,4 +1,4 @@
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# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
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# RUN: llc -O0 %s -o - 2>&1 | FileCheck %s
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# This test ensures that the pseudo expander can correctly handle the case
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# where we are expanding a 16-bit LDD instruction where the source and
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@ -9,25 +9,26 @@
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--- |
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target triple = "avr--"
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define void @test_lddw() {
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entry:
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ret void
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}
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...
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...
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---
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name: test_lddw
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registers:
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- { id: 0, class: _ }
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stack:
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- { id: 0, type: spill-slot, offset: -4, size: 1, alignment: 1, callee-saved-register: '%r28' }
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body: |
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; CHECK-LABEL: bb.0.entry
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bb.0.entry:
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liveins: %r28, %r29
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; CHECK-NEXT: early-clobber %r0 = LDDRdPtrQ %r29r28, 1
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; CHECK-NEXT: PUSHRr %r0, implicit-def %sp, implicit %sp
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; CHECK-NEXT: early-clobber %r0 = LDDRdPtrQ %r29r28, 2
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; CHECK-NEXT: MOVRdRr %r29, %r0
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; CHECK-NEXT: POPRd %r28, implicit-def %sp, implicit %sp
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; CHECK-LABEL: test_lddw
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early-clobber %r29r28 = LDDWRdYQ %r29r28, 1
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; CHECK: ldd [[TMPREG:r[0-9]+]], Y+0
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; CHECK-NEXT: mov r28, [[TMPREG]]
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; CHECK-NEXT: ldd [[TMPREG]], Y+1
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; CHECK-NEXT: mov r29, [[TMPREG]]
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dead early-clobber %r29r28 = LDDWRdYQ killed %r29r28, 0
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...
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