From 5c8510fdc8853c9b0ff77d37aa45f82a45424c0a Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 3 Feb 2017 20:49:48 +0000 Subject: [PATCH] AMDGPU: Cleanup scalar_to_vector test llvm-svn: 294038 --- llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | 26 ++++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll index 32df16778a91..f8f21af5bdaf 100644 --- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll +++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; XXX - Why the packing? -; FUNC-LABEL: {{^}}scalar_to_vector_v2i32: -; SI: buffer_load_dword [[VAL:v[0-9]+]], -; SI: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 16, [[VAL]] -; SI: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[SHR]] -; SI: v_or_b32_e32 v[[OR:[0-9]+]], [[SHL]], [[SHR]] -; SI: v_mov_b32_e32 v[[COPY:[0-9]+]], v[[OR]] -; SI: buffer_store_dwordx2 v{{\[}}[[OR]]:[[COPY]]{{\]}} +; GCN-LABEL: {{^}}scalar_to_vector_v2i32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], +; GCN: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 16, [[VAL]] +; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[SHR]] +; GCN: v_or_b32_e32 v[[OR:[0-9]+]], [[SHL]], [[SHR]] +; GCN: v_mov_b32_e32 v[[COPY:[0-9]+]], v[[OR]] +; GCN: buffer_store_dwordx2 v{{\[}}[[OR]]:[[COPY]]{{\]}} define void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %tmp1 = load i32, i32 addrspace(1)* %in, align 4 %bc = bitcast i32 %tmp1 to <2 x i16> @@ -17,10 +17,10 @@ define void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace( ret void } -; FUNC-LABEL: {{^}}scalar_to_vector_v2f32: -; SI: buffer_load_dword [[VAL:v[0-9]+]], -; SI: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]] -; SI: buffer_store_dwordx2 +; GCN-LABEL: {{^}}scalar_to_vector_v2f32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], +; GCN: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]] +; GCN: buffer_store_dwordx2 define void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind { %tmp1 = load float, float addrspace(1)* %in, align 4 %bc = bitcast float %tmp1 to <2 x i16>