diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 3e3b0eeb6c09..c609ee6174db 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -292,10 +292,10 @@ def ccop : ImmutablePredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
   let PrintMethod = "printPredicateOperand";
 }
 
-// Conditional code result for cmp, etc.
+// Conditional code result for instructions whose 's' bit is set, e.g. subs.
 //
-def cc_out : PredicateDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
-  let PrintMethod = "printPredicateOperand";
+def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
+  let PrintMethod = "printSBitModifierOperand";
 }
 
 //===----------------------------------------------------------------------===//