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Tidy up spacing in LowerVECTOR_SHUFFLEtoBlend. Remove code that checks if shuffle operand has a different type than the the shuffle result since it can never happen. 

llvm-svn: 155333
This commit is contained in:
Craig Topper 2012-04-23 06:38:28 +00:00
parent a52f0d09b6
commit 5c51eeecfc
1 changed files with 34 additions and 39 deletions
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73
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -5390,75 +5390,70 @@ X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
} }
// Try to lower a shuffle node into a simple blend instruction. // Try to lower a shuffle node into a simple blend instruction.
static SDValue LowerVECTOR_SHUFFLEtoBlend(SDValue Op, static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
const X86Subtarget *Subtarget, const X86Subtarget *Subtarget,
SelectionDAG &DAG) { SelectionDAG &DAG) {
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
SDValue V1 = SVOp->getOperand(0); SDValue V1 = SVOp->getOperand(0);
SDValue V2 = SVOp->getOperand(1); SDValue V2 = SVOp->getOperand(1);
DebugLoc dl = SVOp->getDebugLoc(); DebugLoc dl = SVOp->getDebugLoc();
EVT VT = Op.getValueType(); EVT VT = SVOp->getValueType(0);
EVT InVT = V1.getValueType(); unsigned NumElems = VT.getVectorNumElements();
int MaskSize = VT.getVectorNumElements();
int InSize = InVT.getVectorNumElements();
if (!Subtarget->hasSSE41()) if (!Subtarget->hasSSE41())
return SDValue(); return SDValue();
if (MaskSize != InSize) unsigned ISDNo = 0;
return SDValue();
int ISDNo = 0;
MVT OpTy; MVT OpTy;
switch (VT.getSimpleVT().SimpleTy) { switch (VT.getSimpleVT().SimpleTy) {
default: return SDValue(); default: return SDValue();
case MVT::v8i16: case MVT::v8i16:
ISDNo = X86ISD::BLENDPW; ISDNo = X86ISD::BLENDPW;
OpTy = MVT::v8i16; OpTy = MVT::v8i16;
break; break;
case MVT::v4i32: case MVT::v4i32:
case MVT::v4f32: case MVT::v4f32:
ISDNo = X86ISD::BLENDPS; ISDNo = X86ISD::BLENDPS;
OpTy = MVT::v4f32; OpTy = MVT::v4f32;
break; break;
case MVT::v2i64: case MVT::v2i64:
case MVT::v2f64: case MVT::v2f64:
ISDNo = X86ISD::BLENDPD; ISDNo = X86ISD::BLENDPD;
OpTy = MVT::v2f64; OpTy = MVT::v2f64;
break; break;
case MVT::v8i32: case MVT::v8i32:
case MVT::v8f32: case MVT::v8f32:
if (!Subtarget->hasAVX()) if (!Subtarget->hasAVX())
return SDValue(); return SDValue();
ISDNo = X86ISD::BLENDPS; ISDNo = X86ISD::BLENDPS;
OpTy = MVT::v8f32; OpTy = MVT::v8f32;
break; break;
case MVT::v4i64: case MVT::v4i64:
case MVT::v4f64: case MVT::v4f64:
if (!Subtarget->hasAVX()) if (!Subtarget->hasAVX())
return SDValue(); return SDValue();
ISDNo = X86ISD::BLENDPD; ISDNo = X86ISD::BLENDPD;
OpTy = MVT::v4f64; OpTy = MVT::v4f64;
break; break;
case MVT::v16i16: case MVT::v16i16:
if (!Subtarget->hasAVX2()) if (!Subtarget->hasAVX2())
return SDValue(); return SDValue();
ISDNo = X86ISD::BLENDPW; ISDNo = X86ISD::BLENDPW;
OpTy = MVT::v16i16; OpTy = MVT::v16i16;
break; break;
} }
assert(ISDNo && "Invalid Op Number"); assert(ISDNo && "Invalid Op Number");
unsigned MaskVals = 0; unsigned MaskVals = 0;
for (int i = 0; i < MaskSize; ++i) { for (unsigned i = 0; i != NumElems; ++i) {
int EltIdx = SVOp->getMaskElt(i); int EltIdx = SVOp->getMaskElt(i);
if (EltIdx == i || EltIdx == -1) if (EltIdx == (int)i || EltIdx < 0)
MaskVals |= (1<<i); MaskVals |= (1<<i);
else if (EltIdx == (i + MaskSize)) else if (EltIdx == (int)(i + NumElems))
continue; // Bit is set to zero; continue; // Bit is set to zero;
else return SDValue(); else
return SDValue();
} }
V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1); V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
@ -6626,7 +6621,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1, return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
V2, getShuffleVPERM2X128Immediate(SVOp), DAG); V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(Op, Subtarget, DAG); SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
if (BlendOp.getNode()) if (BlendOp.getNode())
return BlendOp; return BlendOp;