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[RISCV] Implement isLegalAddImmediate 

This causes a trivial improvement in the recently added lsr-legaladdimm.ll 
test case.

llvm-svn: 330937
This commit is contained in:
Alex Bradbury 2018-04-26 13:00:37 +00:00
parent c2f78f80da
commit 5c41ecedf8
3 changed files with 16 additions and 12 deletions
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4
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -183,6 +183,10 @@ bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL,
return true; return true;
} }
bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const {
return isInt<12>(Imm);
}
// Changes the condition code and swaps operands if necessary, so the SetCC // Changes the condition code and swaps operands if necessary, so the SetCC
// operation matches one of the comparisons supported directly in the RISC-V // operation matches one of the comparisons supported directly in the RISC-V
// ISA. // ISA.

1
llvm/lib/Target/RISCV/RISCVISelLowering.h
View File

@ -42,6 +42,7 @@ public:
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
unsigned AS, unsigned AS,
Instruction *I = nullptr) const override; Instruction *I = nullptr) const override;
bool isLegalAddImmediate(int64_t Imm) const override;
// Provide custom lowering hooks for some operations. // Provide custom lowering hooks for some operations.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;

23
llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
View File

@ -11,22 +11,21 @@
define i32 @main() nounwind { define i32 @main() nounwind {
; RV32I-LABEL: main: ; RV32I-LABEL: main:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi a0, zero, -2048 ; RV32I-NEXT: lui a0, %hi(b)
; RV32I-NEXT: lui a1, %hi(b) ; RV32I-NEXT: addi a0, a0, %lo(b)
; RV32I-NEXT: addi a1, a1, %lo(b) ; RV32I-NEXT: lui a1, %hi(a)
; RV32I-NEXT: lui a2, %hi(a) ; RV32I-NEXT: addi a1, a1, %lo(a)
; RV32I-NEXT: addi a2, a2, %lo(a) ; RV32I-NEXT: lui a2, 1
; RV32I-NEXT: lui a3, 1 ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: addi a3, a3, -2048
; RV32I-NEXT: .LBB0_1: # %for.body ; RV32I-NEXT: .LBB0_1: # %for.body
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: sw a0, 0(a2) ; RV32I-NEXT: addi a4, a3, -2048
; RV32I-NEXT: add a4, a0, a3
; RV32I-NEXT: sw a4, 0(a1) ; RV32I-NEXT: sw a4, 0(a1)
; RV32I-NEXT: addi a2, a2, 4
; RV32I-NEXT: addi a1, a1, 4 ; RV32I-NEXT: addi a1, a1, 4
; RV32I-NEXT: addi a0, a0, 1 ; RV32I-NEXT: sw a3, 0(a0)
; RV32I-NEXT: bne a0, a3, .LBB0_1 ; RV32I-NEXT: addi a0, a0, 4
; RV32I-NEXT: addi a3, a3, 1
; RV32I-NEXT: bne a3, a2, .LBB0_1
; RV32I-NEXT: # %bb.2: # %for.end ; RV32I-NEXT: # %bb.2: # %for.end
; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret ; RV32I-NEXT: ret