Add LiveIntervalUnion print methods, RegAllocGreedy::trySplit debug spew.

llvm-svn: 121783

llvm/lib/CodeGen/LiveIntervalUnion.cpp

@@ -20,8 +20,6 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 
-#include <algorithm>
-
 using namespace llvm;
 
 
@@ -72,11 +70,34 @@ void
 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
   OS << "LIU ";
   TRI->printReg(RepReg, OS);
+  if (empty()) {
+    OS << " empty\n";
+    return;
+  }
   for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
     OS << " [" << SI.start() << ' ' << SI.stop() << "):";
     TRI->printReg(SI.value()->reg, OS);
   }
-  OS << "\n";
+  OS << '\n';
+}
+
+void LiveIntervalUnion::InterferenceResult::print(raw_ostream &OS,
+                                          const TargetRegisterInfo *TRI) const {
+  OS << '[' << start() << ';' << stop() << ")\t";
+  interference()->print(OS, TRI);
+}
+
+void LiveIntervalUnion::Query::print(raw_ostream &OS,
+                                     const TargetRegisterInfo *TRI) {
+  OS << "Interferences with ";
+  LiveUnion->print(OS, TRI);
+  InterferenceResult IR = firstInterference();
+  while (isInterference(IR)) {
+    OS << "  ";
+    IR.print(OS, TRI);
+    OS << '\n';
+    nextInterference(IR);
+  }
 }
 
 #ifndef NDEBUG

llvm/lib/CodeGen/LiveIntervalUnion.h

@@ -20,6 +20,8 @@
 #include "llvm/ADT/IntervalMap.h"
 #include "llvm/CodeGen/LiveInterval.h"
 
+#include <algorithm>
+
 namespace llvm {
 
 class TargetRegisterInfo;
@@ -71,8 +73,8 @@ public:
   SegmentIter begin() { return Segments.begin(); }
   SegmentIter end() { return Segments.end(); }
   SegmentIter find(SlotIndex x) { return Segments.find(x); }
-  bool empty() { return Segments.empty(); }
-  SlotIndex startIndex() { return Segments.start(); }
+  bool empty() const { return Segments.empty(); }
+  SlotIndex startIndex() const { return Segments.start(); }
 
   // Add a live virtual register to this union and merge its segments.
   void unify(LiveInterval &VirtReg);
@@ -106,6 +108,19 @@ public:
     // Public default ctor.
     InterferenceResult(): VirtRegI(), LiveUnionI() {}
 
+    /// start - Return the start of the current overlap.
+    SlotIndex start() const {
+      return std::max(VirtRegI->start, LiveUnionI.start());
+    }
+
+    /// stop - Return the end of the current overlap.
+    SlotIndex stop() const {
+      return std::min(VirtRegI->end, LiveUnionI.stop());
+    }
+
+    /// interference - Return the register that is interfering here.
+    LiveInterval *interference() const { return LiveUnionI.value(); }
+
     // Note: this interface provides raw access to the iterators because the
     // result has no way to tell if it's valid to dereference them.
 
@@ -121,6 +136,8 @@ public:
     bool operator!=(const InterferenceResult &IR) const {
       return !operator==(IR);
     }
+
+    void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
   };
 
   /// Query interferences between a single live virtual register and a live
@@ -206,6 +223,7 @@ public:
       return InterferingVRegs;
     }
 
+    void print(raw_ostream &OS, const TargetRegisterInfo *TRI);
   private:
     Query(const Query&);          // DO NOT IMPLEMENT
     void operator=(const Query&); // DO NOT IMPLEMENT

llvm/lib/CodeGen/RegAllocGreedy.cpp

@@ -269,6 +269,14 @@ unsigned RAGreedy::tryReassign(LiveInterval &VirtReg, AllocationOrder &Order) {
 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
                             SmallVectorImpl<LiveInterval*>&SplitVRegs) {
   NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
+  Order.rewind();
+  while (unsigned PhysReg = Order.next()) {
+    DEBUG({
+      query(VirtReg, PhysReg).print(dbgs(), TRI);
+      for (const unsigned *AI = TRI->getAliasSet(PhysReg); *AI; ++AI)
+        query(VirtReg, *AI).print(dbgs(), TRI);
+    });
+  }
   return 0;
 }