[SDAG] Minor code cleanup/standardization of atomic accessors [NFC]

llvm-svn: 369057

llvm/include/llvm/CodeGen/SelectionDAGNodes.h

@@ -1351,6 +1351,14 @@ public:
   /// store occurs.
   AtomicOrdering getOrdering() const { return MMO->getOrdering(); }
 
+  /// Return true if the memory operation ordering is Unordered or higher.
+  bool isAtomic() const { return MMO->isAtomic(); }
+
+  /// Returns true if the memory operation doesn't imply any ordering
+  /// constraints on surrounding memory operations beyond the normal memory
+  /// aliasing rules.
+  bool isUnordered() const { return MMO->isUnordered(); }
+
   /// Return the type of the in-memory value.
   EVT getMemoryVT() const { return MemoryVT; }
 

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

@@ -1237,7 +1237,7 @@ bool AArch64InstructionSelector::earlySelectLoad(
 
   // Don't handle atomic loads/stores yet.
   auto &MemOp = **I.memoperands_begin();
-  if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
+  if (MemOp.isAtomic()) {
     LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n");
     return false;
   }
@@ -1739,7 +1739,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
     }
 
     auto &MemOp = **I.memoperands_begin();
-    if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
+    if (MemOp.isAtomic()) {
       // For now we just support s8 acquire loads to be able to compile stack
       // protector code.
       if (MemOp.getOrdering() == AtomicOrdering::Acquire &&

llvm/lib/Target/ARM/ARMInstructionSelector.cpp

@@ -1076,7 +1076,7 @@ bool ARMInstructionSelector::select(MachineInstr &I) {
   case G_STORE:
   case G_LOAD: {
     const auto &MemOp = **I.memoperands_begin();
-    if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) {
+    if (MemOp.isAtomic()) {
       LLVM_DEBUG(dbgs() << "Atomic load/store not supported yet\n");
       return false;
     }