forked from OSchip/llvm-project
[Hexagon] Don't call getNumImplicitDefs and then iterate over the count. getNumImplicitDefs contains a loop so its better to just loop over the null terminated implicit def list. NFC
llvm-svn: 254852
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@ -85,32 +85,33 @@ void HexagonMCChecker::init(MCInst const& MCI) {
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}
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// Get implicit register definitions.
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const MCPhysReg *ImpDefs = MCID.getImplicitDefs();
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for (unsigned i = 0; i < MCID.getNumImplicitDefs(); ++i) {
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unsigned R = ImpDefs[i];
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if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
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for (; *ImpDef; ++ImpDef) {
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unsigned R = *ImpDef;
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if (Hexagon::R31 != R && MCID.isCall())
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// Any register other than the LR and the PC are actually volatile ones
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// as defined by the ABI, not modified implicitly by the call insn.
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continue;
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if (Hexagon::PC == R)
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// Branches are the only insns that can change the PC,
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// otherwise a read-only register.
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continue;
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if (Hexagon::R31 != R && MCID.isCall())
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// Any register other than the LR and the PC are actually volatile ones
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// as defined by the ABI, not modified implicitly by the call insn.
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continue;
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if (Hexagon::PC == R)
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// Branches are the only insns that can change the PC,
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// otherwise a read-only register.
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continue;
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if (Hexagon::USR_OVF == R)
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// Many insns change the USR implicitly, but only one or another flag.
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// The instruction table models the USR.OVF flag, which can be implicitly
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// modified more than once, but cannot be modified in the same packet
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// with an instruction that modifies is explicitly. Deal with such situ-
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// ations individually.
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SoftDefs.insert(R);
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else if (isPredicateRegister(R) && HexagonMCInstrInfo::isPredicateLate(MCII, MCI))
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// Include implicit late predicates.
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LatePreds.insert(R);
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else
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Defs[R].insert(PredSense(PredReg, isTrue));
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}
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if (Hexagon::USR_OVF == R)
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// Many insns change the USR implicitly, but only one or another flag.
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// The instruction table models the USR.OVF flag, which can be implicitly
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// modified more than once, but cannot be modified in the same packet
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// with an instruction that modifies is explicitly. Deal with such situ-
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// ations individually.
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SoftDefs.insert(R);
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else if (isPredicateRegister(R) &&
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HexagonMCInstrInfo::isPredicateLate(MCII, MCI))
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// Include implicit late predicates.
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LatePreds.insert(R);
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else
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Defs[R].insert(PredSense(PredReg, isTrue));
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}
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// Figure out explicit register definitions.
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for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
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