forked from OSchip/llvm-project
RegUsageInfo: Cleanup; NFC
- Remove unnecessary anchor function - Remove unnecessary override of getAnalysisUsage - Use reference instead of pointers where things cannot be nullptr - Use ArrayRef instead of std::vector where possible llvm-svn: 337989
This commit is contained in:
Matthias Braun
parent
bde0806d5f
commit
5c1e23b2e3
|
|
@ -19,6 +19,7 @@
|
|||
#ifndef LLVM_CODEGEN_PHYSICALREGISTERUSAGEINFO_H
|
||||
#define LLVM_CODEGEN_PHYSICALREGISTERUSAGEINFO_H
|
||||
|
||||
#include "llvm/ADT/ArrayRef.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/IR/Instructions.h"
|
||||
#include "llvm/Pass.h"
|
||||
|
|
@ -31,8 +32,6 @@ class Function;
|
|||
class TargetMachine;
|
||||
|
||||
class PhysicalRegisterUsageInfo : public ImmutablePass {
|
||||
virtual void anchor();
|
||||
|
||||
public:
|
||||
static char ID;
|
||||
|
||||
|
|
@ -41,25 +40,20 @@ public:
|
|||
initializePhysicalRegisterUsageInfoPass(Registry);
|
||||
}
|
||||
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
AU.setPreservesAll();
|
||||
}
|
||||
|
||||
/// To set TargetMachine *, which is used to print
|
||||
/// analysis when command line option -print-regusage is used.
|
||||
void setTargetMachine(const TargetMachine *TM_) { TM = TM_; }
|
||||
/// Set TargetMachine which is used to print analysis.
|
||||
void setTargetMachine(const TargetMachine &TM);
|
||||
|
||||
bool doInitialization(Module &M) override;
|
||||
|
||||
bool doFinalization(Module &M) override;
|
||||
|
||||
/// To store RegMask for given Function *.
|
||||
void storeUpdateRegUsageInfo(const Function *FP,
|
||||
std::vector<uint32_t> RegMask);
|
||||
void storeUpdateRegUsageInfo(const Function &FP,
|
||||
ArrayRef<uint32_t> RegMask);
|
||||
|
||||
/// To query stored RegMask for given Function *, it will return nullptr if
|
||||
/// function is not known.
|
||||
const std::vector<uint32_t> *getRegUsageInfo(const Function *FP);
|
||||
/// To query stored RegMask for given Function *, it will returns ane empty
|
||||
/// array if function is not known.
|
||||
ArrayRef<uint32_t> getRegUsageInfo(const Function &FP);
|
||||
|
||||
void print(raw_ostream &OS, const Module *M = nullptr) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -329,6 +329,8 @@ void initializeReassociateLegacyPassPass(PassRegistry&);
|
|||
void initializeRegAllocFastPass(PassRegistry&);
|
||||
void initializeRegBankSelectPass(PassRegistry&);
|
||||
void initializeRegToMemPass(PassRegistry&);
|
||||
void initializeRegUsageInfoCollectorPass(PassRegistry&);
|
||||
void initializeRegUsageInfoPropagationPass(PassRegistry&);
|
||||
void initializeRegionInfoPassPass(PassRegistry&);
|
||||
void initializeRegionOnlyPrinterPass(PassRegistry&);
|
||||
void initializeRegionOnlyViewerPass(PassRegistry&);
|
||||
|
|
|
|||
|
|
@ -85,6 +85,8 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
|
|||
initializeRABasicPass(Registry);
|
||||
initializeRAGreedyPass(Registry);
|
||||
initializeRegAllocFastPass(Registry);
|
||||
initializeRegUsageInfoCollectorPass(Registry);
|
||||
initializeRegUsageInfoPropagationPass(Registry);
|
||||
initializeRegisterCoalescerPass(Registry);
|
||||
initializeRenameIndependentSubregsPass(Registry);
|
||||
initializeSafeStackLegacyPassPass(Registry);
|
||||
|
|
|
|||
|
|
@ -36,11 +36,8 @@ using namespace llvm;
|
|||
STATISTIC(NumCSROpt,
|
||||
"Number of functions optimized for callee saved registers");
|
||||
|
||||
namespace llvm {
|
||||
void initializeRegUsageInfoCollectorPass(PassRegistry &);
|
||||
}
|
||||
|
||||
namespace {
|
||||
|
||||
class RegUsageInfoCollector : public MachineFunctionPass {
|
||||
public:
|
||||
RegUsageInfoCollector() : MachineFunctionPass(ID) {
|
||||
|
|
@ -52,7 +49,11 @@ public:
|
|||
return "Register Usage Information Collector Pass";
|
||||
}
|
||||
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
AU.addRequired<PhysicalRegisterUsageInfo>();
|
||||
AU.setPreservesAll();
|
||||
MachineFunctionPass::getAnalysisUsage(AU);
|
||||
}
|
||||
|
||||
bool runOnMachineFunction(MachineFunction &MF) override;
|
||||
|
||||
|
|
@ -62,6 +63,7 @@ public:
|
|||
|
||||
static char ID;
|
||||
};
|
||||
|
||||
} // end of anonymous namespace
|
||||
|
||||
char RegUsageInfoCollector::ID = 0;
|
||||
|
|
@ -76,12 +78,6 @@ FunctionPass *llvm::createRegUsageInfoCollector() {
|
|||
return new RegUsageInfoCollector();
|
||||
}
|
||||
|
||||
void RegUsageInfoCollector::getAnalysisUsage(AnalysisUsage &AU) const {
|
||||
AU.addRequired<PhysicalRegisterUsageInfo>();
|
||||
AU.setPreservesAll();
|
||||
MachineFunctionPass::getAnalysisUsage(AU);
|
||||
}
|
||||
|
||||
bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
|
||||
MachineRegisterInfo *MRI = &MF.getRegInfo();
|
||||
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
||||
|
|
@ -97,13 +93,12 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
|
|||
// The bit vector is broken into 32-bit chunks, thus takes the ceil of
|
||||
// the number of registers divided by 32 for the size.
|
||||
unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
|
||||
RegMask.resize(RegMaskSize, 0xFFFFFFFF);
|
||||
RegMask.resize(RegMaskSize, ~((uint32_t)0));
|
||||
|
||||
const Function &F = MF.getFunction();
|
||||
|
||||
PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
|
||||
|
||||
PRUI->setTargetMachine(&TM);
|
||||
PhysicalRegisterUsageInfo &PRUI = getAnalysis<PhysicalRegisterUsageInfo>();
|
||||
PRUI.setTargetMachine(TM);
|
||||
|
||||
LLVM_DEBUG(dbgs() << "Clobbered Registers: ");
|
||||
|
||||
|
|
@ -147,37 +142,37 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
|
|||
|
||||
LLVM_DEBUG(dbgs() << " \n----------------------------------------\n");
|
||||
|
||||
PRUI->storeUpdateRegUsageInfo(&F, std::move(RegMask));
|
||||
PRUI.storeUpdateRegUsageInfo(F, RegMask);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void RegUsageInfoCollector::
|
||||
computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
|
||||
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
|
||||
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
|
||||
const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
|
||||
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
|
||||
|
||||
// Target will return the set of registers that it saves/restores as needed.
|
||||
SavedRegs.clear();
|
||||
TFI->determineCalleeSaves(MF, SavedRegs);
|
||||
TFI.determineCalleeSaves(MF, SavedRegs);
|
||||
|
||||
// Insert subregs.
|
||||
const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
|
||||
const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
|
||||
for (unsigned i = 0; CSRegs[i]; ++i) {
|
||||
unsigned Reg = CSRegs[i];
|
||||
if (SavedRegs.test(Reg))
|
||||
for (MCSubRegIterator SR(Reg, TRI, false); SR.isValid(); ++SR)
|
||||
for (MCSubRegIterator SR(Reg, &TRI, false); SR.isValid(); ++SR)
|
||||
SavedRegs.set(*SR);
|
||||
}
|
||||
|
||||
// Insert any register fully saved via subregisters.
|
||||
for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
|
||||
for (unsigned PReg = 1, PRegE = TRI.getNumRegs(); PReg < PRegE; ++PReg) {
|
||||
if (SavedRegs.test(PReg))
|
||||
continue;
|
||||
|
||||
// Check if PReg is fully covered by its subregs.
|
||||
bool CoveredBySubRegs = false;
|
||||
for (const TargetRegisterClass *RC : TRI->regclasses())
|
||||
for (const TargetRegisterClass *RC : TRI.regclasses())
|
||||
if (RC->CoveredBySubRegs && RC->contains(PReg)) {
|
||||
CoveredBySubRegs = true;
|
||||
break;
|
||||
|
|
@ -187,7 +182,7 @@ computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
|
|||
|
||||
// Add PReg to SavedRegs if all subregs are saved.
|
||||
bool AllSubRegsSaved = true;
|
||||
for (MCSubRegIterator SR(PReg, TRI, false); SR.isValid(); ++SR)
|
||||
for (MCSubRegIterator SR(PReg, &TRI, false); SR.isValid(); ++SR)
|
||||
if (!SavedRegs.test(*SR)) {
|
||||
AllSubRegsSaved = false;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -34,10 +34,6 @@
|
|||
#include <map>
|
||||
#include <string>
|
||||
|
||||
namespace llvm {
|
||||
void initializeRegUsageInfoPropagationPassPass(PassRegistry &);
|
||||
}
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "ip-regalloc"
|
||||
|
|
@ -45,54 +41,56 @@ using namespace llvm;
|
|||
#define RUIP_NAME "Register Usage Information Propagation"
|
||||
|
||||
namespace {
|
||||
class RegUsageInfoPropagationPass : public MachineFunctionPass {
|
||||
|
||||
class RegUsageInfoPropagation : public MachineFunctionPass {
|
||||
public:
|
||||
RegUsageInfoPropagationPass() : MachineFunctionPass(ID) {
|
||||
RegUsageInfoPropagation() : MachineFunctionPass(ID) {
|
||||
PassRegistry &Registry = *PassRegistry::getPassRegistry();
|
||||
initializeRegUsageInfoPropagationPassPass(Registry);
|
||||
initializeRegUsageInfoPropagationPass(Registry);
|
||||
}
|
||||
|
||||
StringRef getPassName() const override { return RUIP_NAME; }
|
||||
|
||||
bool runOnMachineFunction(MachineFunction &MF) override;
|
||||
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
AU.addRequired<PhysicalRegisterUsageInfo>();
|
||||
AU.setPreservesAll();
|
||||
MachineFunctionPass::getAnalysisUsage(AU);
|
||||
}
|
||||
|
||||
static char ID;
|
||||
|
||||
private:
|
||||
static void setRegMask(MachineInstr &MI, const uint32_t *RegMask) {
|
||||
static void setRegMask(MachineInstr &MI, ArrayRef<uint32_t> RegMask) {
|
||||
assert(RegMask.size() ==
|
||||
MachineOperand::getRegMaskSize(MI.getParent()->getParent()
|
||||
->getRegInfo().getTargetRegisterInfo()
|
||||
->getNumRegs())
|
||||
&& "expected register mask size");
|
||||
for (MachineOperand &MO : MI.operands()) {
|
||||
if (MO.isRegMask())
|
||||
MO.setRegMask(RegMask);
|
||||
MO.setRegMask(RegMask.data());
|
||||
}
|
||||
}
|
||||
};
|
||||
} // end of anonymous namespace
|
||||
char RegUsageInfoPropagationPass::ID = 0;
|
||||
|
||||
INITIALIZE_PASS_BEGIN(RegUsageInfoPropagationPass, "reg-usage-propagation",
|
||||
} // end of anonymous namespace
|
||||
|
||||
INITIALIZE_PASS_BEGIN(RegUsageInfoPropagation, "reg-usage-propagation",
|
||||
RUIP_NAME, false, false)
|
||||
INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo)
|
||||
INITIALIZE_PASS_END(RegUsageInfoPropagationPass, "reg-usage-propagation",
|
||||
INITIALIZE_PASS_END(RegUsageInfoPropagation, "reg-usage-propagation",
|
||||
RUIP_NAME, false, false)
|
||||
|
||||
FunctionPass *llvm::createRegUsageInfoPropPass() {
|
||||
return new RegUsageInfoPropagationPass();
|
||||
}
|
||||
|
||||
void RegUsageInfoPropagationPass::getAnalysisUsage(AnalysisUsage &AU) const {
|
||||
AU.addRequired<PhysicalRegisterUsageInfo>();
|
||||
AU.setPreservesAll();
|
||||
MachineFunctionPass::getAnalysisUsage(AU);
|
||||
}
|
||||
char RegUsageInfoPropagation::ID = 0;
|
||||
|
||||
// Assumes call instructions have a single reference to a function.
|
||||
static const Function *findCalledFunction(const Module &M, MachineInstr &MI) {
|
||||
for (MachineOperand &MO : MI.operands()) {
|
||||
static const Function *findCalledFunction(const Module &M,
|
||||
const MachineInstr &MI) {
|
||||
for (const MachineOperand &MO : MI.operands()) {
|
||||
if (MO.isGlobal())
|
||||
return dyn_cast<Function>(MO.getGlobal());
|
||||
return dyn_cast<const Function>(MO.getGlobal());
|
||||
|
||||
if (MO.isSymbol())
|
||||
return M.getFunction(MO.getSymbolName());
|
||||
|
|
@ -101,8 +99,8 @@ static const Function *findCalledFunction(const Module &M, MachineInstr &MI) {
|
|||
return nullptr;
|
||||
}
|
||||
|
||||
bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) {
|
||||
const Module *M = MF.getFunction().getParent();
|
||||
bool RegUsageInfoPropagation::runOnMachineFunction(MachineFunction &MF) {
|
||||
const Module &M = *MF.getFunction().getParent();
|
||||
PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
|
||||
|
||||
LLVM_DEBUG(dbgs() << " ++++++++++++++++++++ " << getPassName()
|
||||
|
|
@ -124,16 +122,16 @@ bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) {
|
|||
<< "Call Instruction Before Register Usage Info Propagation : \n");
|
||||
LLVM_DEBUG(dbgs() << MI << "\n");
|
||||
|
||||
auto UpdateRegMask = [&](const Function *F) {
|
||||
const auto *RegMask = PRUI->getRegUsageInfo(F);
|
||||
if (!RegMask)
|
||||
auto UpdateRegMask = [&](const Function &F) {
|
||||
const ArrayRef<uint32_t> RegMask = PRUI->getRegUsageInfo(F);
|
||||
if (RegMask.empty())
|
||||
return;
|
||||
setRegMask(MI, &(*RegMask)[0]);
|
||||
setRegMask(MI, RegMask);
|
||||
Changed = true;
|
||||
};
|
||||
|
||||
if (const Function *F = findCalledFunction(*M, MI)) {
|
||||
UpdateRegMask(F);
|
||||
if (const Function *F = findCalledFunction(M, MI)) {
|
||||
UpdateRegMask(*F);
|
||||
} else {
|
||||
LLVM_DEBUG(dbgs() << "Failed to find call target function\n");
|
||||
}
|
||||
|
|
@ -149,3 +147,7 @@ bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) {
|
|||
"++++++ \n");
|
||||
return Changed;
|
||||
}
|
||||
|
||||
FunctionPass *llvm::createRegUsageInfoPropPass() {
|
||||
return new RegUsageInfoPropagation();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,8 +31,6 @@
|
|||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "ip-regalloc"
|
||||
|
||||
static cl::opt<bool> DumpRegUsage(
|
||||
"print-regusage", cl::init(false), cl::Hidden,
|
||||
cl::desc("print register usage details collected for analysis."));
|
||||
|
|
@ -42,7 +40,9 @@ INITIALIZE_PASS(PhysicalRegisterUsageInfo, "reg-usage-info",
|
|||
|
||||
char PhysicalRegisterUsageInfo::ID = 0;
|
||||
|
||||
void PhysicalRegisterUsageInfo::anchor() {}
|
||||
void PhysicalRegisterUsageInfo::setTargetMachine(const TargetMachine &TM) {
|
||||
this->TM = &TM;
|
||||
}
|
||||
|
||||
bool PhysicalRegisterUsageInfo::doInitialization(Module &M) {
|
||||
RegMasks.grow(M.size());
|
||||
|
|
@ -58,22 +58,19 @@ bool PhysicalRegisterUsageInfo::doFinalization(Module &M) {
|
|||
}
|
||||
|
||||
void PhysicalRegisterUsageInfo::storeUpdateRegUsageInfo(
|
||||
const Function *FP, std::vector<uint32_t> RegMask) {
|
||||
assert(FP != nullptr && "Function * can't be nullptr.");
|
||||
RegMasks[FP] = std::move(RegMask);
|
||||
const Function &FP, ArrayRef<uint32_t> RegMask) {
|
||||
RegMasks[&FP] = RegMask;
|
||||
}
|
||||
|
||||
const std::vector<uint32_t> *
|
||||
PhysicalRegisterUsageInfo::getRegUsageInfo(const Function *FP) {
|
||||
auto It = RegMasks.find(FP);
|
||||
ArrayRef<uint32_t>
|
||||
PhysicalRegisterUsageInfo::getRegUsageInfo(const Function &FP) {
|
||||
auto It = RegMasks.find(&FP);
|
||||
if (It != RegMasks.end())
|
||||
return &(It->second);
|
||||
return nullptr;
|
||||
return makeArrayRef<uint32_t>(It->second);
|
||||
return ArrayRef<uint32_t>();
|
||||
}
|
||||
|
||||
void PhysicalRegisterUsageInfo::print(raw_ostream &OS, const Module *M) const {
|
||||
const TargetRegisterInfo *TRI;
|
||||
|
||||
using FuncPtrRegMaskPair = std::pair<const Function *, std::vector<uint32_t>>;
|
||||
|
||||
SmallVector<const FuncPtrRegMaskPair *, 64> FPRMPairVector;
|
||||
|
|
@ -92,8 +89,9 @@ void PhysicalRegisterUsageInfo::print(raw_ostream &OS, const Module *M) const {
|
|||
for (const FuncPtrRegMaskPair *FPRMPair : FPRMPairVector) {
|
||||
OS << FPRMPair->first->getName() << " "
|
||||
<< "Clobbered Registers: ";
|
||||
TRI = TM->getSubtarget<TargetSubtargetInfo>(*(FPRMPair->first))
|
||||
.getRegisterInfo();
|
||||
const TargetRegisterInfo *TRI
|
||||
= TM->getSubtarget<TargetSubtargetInfo>(*(FPRMPair->first))
|
||||
.getRegisterInfo();
|
||||
|
||||
for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
|
||||
if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg))
|
||||
|
|
|
|||
Loading…
Reference in New Issue