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[mips][mips64r6] Add BLTC and BLTUC instructions 

Differential Revision: http://reviews.llvm.org/D3923

llvm-svn: 211167
This commit is contained in:
Zoran Jovanovic 2014-06-18 14:36:00 +00:00
parent b87f1efc5f
commit 5c14b06940
6 changed files with 33 additions and 6 deletions
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19
llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@ -576,6 +576,8 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
// BLTZC if rs == rt && rt != 0
// BLTC if rs != rt && rs != 0 && rt != 0
bool HasRs = false;
InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
@ -586,8 +588,14 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
MI.setOpcode(Mips::BGTZC);
else if (Rs == Rt)
MI.setOpcode(Mips::BLTZC);
else
return MCDisassembler::Fail; // FIXME: BLTC is not implemented yet.
else {
MI.setOpcode(Mips::BLTC);
HasRs = true;
}
if (HasRs)
MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
Rs)));
MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
Rt)));
@ -627,8 +635,11 @@ static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
} else if (Rs == Rt) {
MI.setOpcode(Mips::BLTZALC);
HasRs = true;
} else
return MCDisassembler::Fail; // BLTUC not implemented yet
} else {
MI.setOpcode(Mips::BLTUC);
HasRs = true;
HasRt = true;
}
if (HasRs)
MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,

12
llvm/lib/Target/Mips/Mips32r6InstrInfo.td
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@ -77,6 +77,11 @@ class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
DecodeDisambiguatedBy<"BgtzGroupBranch">;
class BLTC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZL>,
DecodeDisambiguatedBy<"BgtzlGroupBranch">;
class BLTUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZ>,
DecodeDisambiguatedBy<"BgtzGroupBranch">;
class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
DecodeDisambiguatedBy<"BlezlGroupBranch">;
class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
@ -329,6 +334,9 @@ class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
@ -636,8 +644,8 @@ def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
def BLTC; // Also aliased to bgtc with operands swapped
def BLTUC; // Also aliased to bgtuc with operands swapped
def BLTC : BLTC_ENC, BLTC_DESC, ISA_MIPS32R6;
def BLTUC : BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6;
def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;

2
llvm/test/MC/Disassembler/Mips/mips32r6.txt
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@ -42,6 +42,8 @@
0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256
0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2
0x18 0x02 0x01 0x4d # CHECK: blezalc $2,
0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256
0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256
0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4
0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4
0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4

2
llvm/test/MC/Disassembler/Mips/mips64r6.txt
View File

@ -42,6 +42,8 @@
0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256
0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2
0x18 0x02 0x01 0x4d # CHECK: blezalc $2,
0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256
0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256
0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4
0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4
0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4

2
llvm/test/MC/Mips/mips32r6/valid.s
View File

@ -53,6 +53,8 @@
bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40]
bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20]
blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0x18,0x02,0x01,0x4d]
bltc $5, $6, 256 # CHECK: bltc $5, $6, 256 # encoding: [0x5c,0xa6,0x00,0x40]
bltuc $5, $6, 256 # CHECK: bltuc $5, $6, 256 # encoding: [0x1c,0xa6,0x00,0x40]
# bnvc requires that rs >= rt but we accept both. See also bnec
bnvc $0, $0, 4 # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01]
bnvc $2, $0, 4 # CHECK: bnvc $2, $zero, 4 # encoding: [0x60,0x40,0x00,0x01]

2
llvm/test/MC/Mips/mips64r6/valid.s
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@ -53,6 +53,8 @@
bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40]
bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20]
blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0x18,0x02,0x01,0x4d]
bltc $5, $6, 256 # CHECK: bltc $5, $6, 256 # encoding: [0x5c,0xa6,0x00,0x40]
bltuc $5, $6, 256 # CHECK: bltuc $5, $6, 256 # encoding: [0x1c,0xa6,0x00,0x40]
# bnvc requires that rs >= rt but we accept both. See also bnec
bnvc $0, $0, 4 # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01]
bnvc $2, $0, 4 # CHECK: bnvc $2, $zero, 4 # encoding: [0x60,0x40,0x00,0x01]