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now that addc/adde are gone, "ADDC" in the X86 backend uses EFLAGS results, 

the same as setcc.  Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS).  This is
a step towards finishing off PR5443.  In the testcase in that bug we now  get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	sbbq	%rcx, %rcx
	testb	$1, %cl
	setne	%dl
	ret

instead of:

	movq	%rdi, %rax
	addq	%rsi, %rax
	movl	$0, %ecx
	adcq	$0, %rcx
	testq	%rcx, %rcx
	setne	%dl
	ret

llvm-svn: 122219
This commit is contained in:
Chris Lattner 2010-12-20 01:37:09 +00:00
parent fc0c6b1ea9
commit 5c00d41688
2 changed files with 46 additions and 0 deletions
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27
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -11493,6 +11493,32 @@ static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
return SDValue();
}
// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
X86TargetLowering::DAGCombinerInfo &DCI) {
// If the LHS and RHS of the ADC node are zero, then it can't overflow and
// the result is either zero or one (depending on the input carry bit).
// Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
if (X86::isZeroNode(N->getOperand(0)) &&
X86::isZeroNode(N->getOperand(1)) &&
// We don't have a good way to replace an EFLAGS use, so only do this when
// dead right now.
SDValue(N, 1).use_empty()) {
DebugLoc DL = N->getDebugLoc();
EVT VT = N->getValueType(0);
SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
DAG.getConstant(X86::COND_B,MVT::i8),
N->getOperand(2)),
DAG.getConstant(1, VT));
return DCI.CombineTo(N, Res1, CarryOut);
}
return SDValue();
}
SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
@ -11503,6 +11529,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
case ISD::SHL:
case ISD::SRA:

19
llvm/test/CodeGen/X86/add.ll
View File

@ -101,3 +101,22 @@ define {i32, i1} @test7(i32 %v1, i32 %v2) nounwind {
; X64: addl %esi, %eax
; X64-NEXT: setb %dl
; X64-NEXT: ret
; PR5443
define {i64, i1} @test8(i64 %left, i64 %right) nounwind {
entry:
%extleft = zext i64 %left to i65
%extright = zext i64 %right to i65
%sum = add i65 %extleft, %extright
%res.0 = trunc i65 %sum to i64
%overflow = and i65 %sum, -18446744073709551616
%res.1 = icmp ne i65 %overflow, 0
%final0 = insertvalue {i64, i1} undef, i64 %res.0, 0
%final1 = insertvalue {i64, i1} %final0, i1 %res.1, 1
ret {i64, i1} %final1
}
; X64: test8:
; X64: addq
; X64-NEXT: sbbq
; X64-NEXT: testb