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Turn sdivs into udivs when we can prove the sign bits are clear. This 

implements CodeGen/PowerPC/div-2.ll

llvm-svn: 23659
This commit is contained in:
Chris Lattner 2005-10-07 06:10:46 +00:00
parent 437b9aa632
commit 5bcd0dd811
2 changed files with 21 additions and 0 deletions
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10
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -501,6 +501,7 @@ SDOperand DAGCombiner::visitMUL(SDNode *N) {
SDOperand DAGCombiner::visitSDIV(SDNode *N) { SDOperand DAGCombiner::visitSDIV(SDNode *N) {
SDOperand N0 = N->getOperand(0); SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1); SDOperand N1 = N->getOperand(1);
MVT::ValueType VT = N->getValueType(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
@ -508,6 +509,15 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
if (N0C && N1C && !N1C->isNullValue()) if (N0C && N1C && !N1C->isNullValue())
return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(), return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
N->getValueType(0)); N->getValueType(0));
// If we know the sign bits of both operands are zero, strength reduce to a
// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
if (MaskedValueIsZero(N1, SignBit, TLI) &&
MaskedValueIsZero(N0, SignBit, TLI))
return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
return SDOperand(); return SDOperand();
} }

11
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1556,6 +1556,17 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
return N1; return N1;
} }
break; break;
case ISD::SDIV: {
if (CombinerEnabled) break;
// If we know the sign bits of both operands are zero, strength reduce to a
// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
if (MaskedValueIsZero(N2, SignBit, TLI) &&
MaskedValueIsZero(N1, SignBit, TLI))
return getNode(ISD::UDIV, VT, N1, N2);
break;
}
case ISD::AND: case ISD::AND:
case ISD::OR: case ISD::OR: