forked from OSchip/llvm-project
parent
11c25cfa13
commit
5bc60da112
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@ -28,13 +28,6 @@
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#include <set>
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using namespace llvm;
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namespace ARMISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
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RET_FLAG
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};
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}
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namespace {
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class ARMTargetLowering : public TargetLowering {
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public:
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@ -63,11 +56,12 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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case 1:
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return SDOperand(); // ret void is legal
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case 3:
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Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(2), SDOperand());
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Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
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break;
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}
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SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
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return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
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return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR);
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}
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static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
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@ -30,10 +30,6 @@ def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]>;
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def SDT_ARMRetFlag : SDTypeProfile<0, 0, []>;
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def retflag : SDNode<"ARMISD::RET_FLAG", SDT_ARMRetFlag,
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[SDNPHasChain, SDNPOptInFlag]>;
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def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
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"!ADJCALLSTACKUP $amt",
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[(callseq_end imm:$amt)]>;
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@ -42,11 +38,7 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start imm:$amt)]>;
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//bx supports other registers as operands. So this looks like a
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//hack. Maybe a ret should be expanded to a "branch lr" and bx
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//declared as a regular instruction
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def BX: InstARM<(ops), "bx lr", [(retflag)]>;
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def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
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def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldr $dst, [$addr]",
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