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[ARM][TypePromotion] Re-generate test checks. NFC 

Tests were missing load/store alignment. One test in casts.ll had
no check lines.
This commit is contained in:
Craig Topper 2021-08-16 13:36:16 -07:00
parent 65bc8ba1a2
commit 5bab1f0952
6 changed files with 24 additions and 14 deletions
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2
llvm/test/Transforms/TypePromotion/ARM/calls.ll
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@ -169,7 +169,7 @@ define hidden i32 @call_return_pointer(i8 zeroext %p_13) local_unnamed_addr #0 {
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i8
; CHECK-NEXT: [[CONV1:%.*]] = zext i8 [[TMP1]] to i16
; CHECK-NEXT: [[CALL:%.*]] = tail call i16** @func_62(i8 zeroext undef, i32 undef, i16 signext [[CONV1]], i32* undef)
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @g_893, i32 0, i32 0), align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_ANON:%.*]], %struct.anon* @g_893, i32 0, i32 0), align 4
; CHECK-NEXT: [[CONV2:%.*]] = trunc i32 [[TMP2]] to i16
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:

20
llvm/test/Transforms/TypePromotion/ARM/casts.ll
View File

@ -32,7 +32,7 @@ define i8 @trunc_i16_i8(i16* %ptr, i16 zeroext %arg0, i8 zeroext %arg1) {
; CHECK-LABEL: @trunc_i16_i8(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[ARG1:%.*]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* [[PTR:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = load i16, i16* [[PTR:%.*]], align 2
; CHECK-NEXT: [[TMP2:%.*]] = add i16 [[TMP1]], [[ARG0:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = trunc i16 [[TMP2]] to i8
; CHECK-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i32
@ -132,7 +132,7 @@ entry:
define i1 @or_icmp_ugt(i32 %arg, i8* %ptr) {
; CHECK-LABEL: @or_icmp_ugt(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[PTR:%.*]]
; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[PTR:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP0]] to i32
; CHECK-NEXT: [[MUL:%.*]] = shl nuw nsw i32 [[TMP2]], 1
@ -246,6 +246,16 @@ exit:
}
define i16 @bitcast_i16(i16 zeroext %arg0, i16 zeroext %arg1) {
; CHECK-LABEL: @bitcast_i16(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[ARG0:%.*]] to i32
; CHECK-NEXT: [[CAST:%.*]] = bitcast i16 12345 to i16
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[CAST]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP0]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ule i32 [[ADD]], [[TMP1]]
; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i16 [[ARG1:%.*]], i16 32657
; CHECK-NEXT: ret i16 [[RES]]
;
entry:
%cast = bitcast i16 12345 to i16
%add = add nuw i16 %arg0, 1
@ -518,7 +528,7 @@ define i8 @search_through_zext_load(i8* %a, i8 zeroext %b, i16 zeroext %c) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[B:%.*]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[C:%.*]] to i32
; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8* [[A:%.*]]
; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8* [[A:%.*]], align 1
; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[LOAD]] to i32
; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[TMP2]], [[TMP1]]
; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
@ -631,7 +641,7 @@ define i16 @trunc_sink_less_than_store(i16 zeroext %a, i16 zeroext %b, i16 zeroe
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[SUB]], 255
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP2]], [[TMP4]]
; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[ADD]] to i8
; CHECK-NEXT: store i8 [[TMP5]], i8* [[E:%.*]]
; CHECK-NEXT: store i8 [[TMP5]], i8* [[E:%.*]], align 1
; CHECK-NEXT: br label [[IF_END]]
; CHECK: if.end:
; CHECK-NEXT: [[RETVAL:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[SUB]], [[IF_THEN]] ]
@ -981,7 +991,7 @@ entry:
define i32 @replace_trunk_with_mask(i16* %a) {
; CHECK-LABEL: @replace_trunk_with_mask(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]]
; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[TMP0]] to i32
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: br i1 [[CMP]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]]

8
llvm/test/Transforms/TypePromotion/ARM/icmps.ll
View File

@ -168,8 +168,8 @@ define void @store_dsp_res(i8* %in, i8* %out, i8 %compare) {
; CHECK-LABEL: @store_dsp_res(
; CHECK-NEXT: [[FIRST:%.*]] = getelementptr inbounds i8, i8* [[IN:%.*]], i32 0
; CHECK-NEXT: [[SECOND:%.*]] = getelementptr inbounds i8, i8* [[IN]], i32 1
; CHECK-NEXT: [[LD0:%.*]] = load i8, i8* [[FIRST]]
; CHECK-NEXT: [[LD1:%.*]] = load i8, i8* [[SECOND]]
; CHECK-NEXT: [[LD0:%.*]] = load i8, i8* [[FIRST]], align 1
; CHECK-NEXT: [[LD1:%.*]] = load i8, i8* [[SECOND]], align 1
; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[LD0]], -1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[COMPARE:%.*]], [[LD1]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[COMPARE]], i8 [[XOR]]
@ -253,7 +253,7 @@ define i32 @icmp_not(i16 zeroext %arg0, i16 zeroext %arg1) {
define i32 @icmp_i1(i1* %arg0, i1 zeroext %arg1, i32 %a, i32 %b) {
; CHECK-LABEL: @icmp_i1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[LOAD:%.*]] = load i1, i1* [[ARG0:%.*]]
; CHECK-NEXT: [[LOAD:%.*]] = load i1, i1* [[ARG0:%.*]], align 1
; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[LOAD]], true
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i1 [[ARG1:%.*]], [[NOT]]
; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP]], i32 [[A:%.*]], i32 [[B:%.*]]
@ -271,7 +271,7 @@ define i32 @icmp_i7(i7* %arg0, i7 zeroext %arg1, i32 %a, i32 %b) {
; CHECK-LABEL: @icmp_i7(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = zext i7 [[ARG1:%.*]] to i32
; CHECK-NEXT: [[LOAD:%.*]] = load i7, i7* [[ARG0:%.*]]
; CHECK-NEXT: [[LOAD:%.*]] = load i7, i7* [[ARG0:%.*]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = zext i7 [[LOAD]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP1]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP0]], [[ADD]]

2
llvm/test/Transforms/TypePromotion/ARM/phis-ret.ll
View File

@ -278,7 +278,7 @@ define i16 @promote_arg_return(i16 zeroext %arg1, i16 zeroext %arg2, i8* %res) {
; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[ADD]], 3
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[MUL]], [[TMP2]]
; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i8
; CHECK-NEXT: store i8 [[CONV]], i8* [[RES:%.*]]
; CHECK-NEXT: store i8 [[CONV]], i8* [[RES:%.*]], align 1
; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP1]] to i16
; CHECK-NEXT: ret i16 [[TMP3]]
;

4
llvm/test/Transforms/TypePromotion/ARM/pointers.ll
View File

@ -130,8 +130,8 @@ define i8 @call_pointer(i8 zeroext %x, i8 zeroext %y, i16* %a, i16* %b) {
define i16 @pointer_to_pointer(i16** %arg, i16 zeroext %limit) {
; CHECK-LABEL: @pointer_to_pointer(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ADDR:%.*]] = load i16*, i16** [[ARG:%.*]]
; CHECK-NEXT: [[VAL:%.*]] = load i16, i16* [[ADDR]]
; CHECK-NEXT: [[ADDR:%.*]] = load i16*, i16** [[ARG:%.*]], align 8
; CHECK-NEXT: [[VAL:%.*]] = load i16, i16* [[ADDR]], align 2
; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[VAL]] to i32
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP0]], 7
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD]], 256

2
llvm/test/Transforms/TypePromotion/ARM/signed.ll
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@ -4,7 +4,7 @@
; Test to check that ARMCodeGenPrepare doesn't optimised away sign extends.
define i16 @test_signed_load(i16* %ptr) {
; CHECK-LABEL: @test_signed_load(
; CHECK-NEXT: [[LOAD:%.*]] = load i16, i16* [[PTR:%.*]]
; CHECK-NEXT: [[LOAD:%.*]] = load i16, i16* [[PTR:%.*]], align 2
; CHECK-NEXT: [[CONV0:%.*]] = zext i16 [[LOAD]] to i32
; CHECK-NEXT: [[CONV1:%.*]] = sext i16 [[LOAD]] to i32
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CONV0]], [[CONV1]]