forked from OSchip/llvm-project
[Hexagon] Use MachineInstrBuilder instead of changing instruction in place
llvm-svn: 305953
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9fa8af6f82
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@ -100,9 +100,6 @@ namespace {
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
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};
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}
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@ -132,7 +129,9 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
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PeepholeDoubleRegsMap.clear();
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// Traverse the basic block.
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for (MachineInstr &MI : *MBB) {
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for (auto I = MBB->begin(), E = MBB->end(), NextI = I; I != E; I = NextI) {
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NextI = std::next(I);
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MachineInstr &MI = *I;
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// Look for sign extends:
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// %vreg170<def> = SXTW %vreg166
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if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) {
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@ -280,14 +279,13 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
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if (NewOp) {
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unsigned PSrc = MI.getOperand(PR).getReg();
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if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
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MI.getOperand(PR).setReg(POrig);
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BuildMI(*MBB, MI.getIterator(), MI.getDebugLoc(),
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QII->get(NewOp), MI.getOperand(0).getReg())
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.addReg(POrig)
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.add(MI.getOperand(S2))
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.add(MI.getOperand(S1));
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MRI->clearKillFlags(POrig);
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MI.setDesc(QII->get(NewOp));
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// Swap operands S1 and S2.
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MachineOperand Op1 = MI.getOperand(S1);
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MachineOperand Op2 = MI.getOperand(S2);
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ChangeOpInto(MI.getOperand(S1), Op2);
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ChangeOpInto(MI.getOperand(S2), Op1);
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MI.eraseFromParent();
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}
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} // if (NewOp)
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} // if (!Done)
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@ -299,40 +297,6 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
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return true;
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}
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void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
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assert (&Dst != &Src && "Cannot duplicate into itself");
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switch (Dst.getType()) {
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case MachineOperand::MO_Register:
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if (Src.isReg()) {
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Dst.setReg(Src.getReg());
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Dst.setSubReg(Src.getSubReg());
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MRI->clearKillFlags(Src.getReg());
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} else if (Src.isImm()) {
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Dst.ChangeToImmediate(Src.getImm());
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} else {
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llvm_unreachable("Unexpected src operand type");
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}
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break;
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case MachineOperand::MO_Immediate:
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if (Src.isImm()) {
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Dst.setImm(Src.getImm());
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} else if (Src.isReg()) {
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Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
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false, Src.isDead(), Src.isUndef(),
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Src.isDebug());
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Dst.setSubReg(Src.getSubReg());
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} else {
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llvm_unreachable("Unexpected src operand type");
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}
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break;
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default:
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llvm_unreachable("Unexpected dst operand type");
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break;
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}
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}
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FunctionPass *llvm::createHexagonPeephole() {
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return new HexagonPeephole();
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}
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