forked from OSchip/llvm-project
[ARM] GlobalISel: Add mapping for G_CONSTANT
Like G_FRAME_INDEX, G_CONSTANT has one register operand and one non-register operand. llvm-svn: 296469
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@ -240,6 +240,7 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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? &ARM::ValueMappings[ARM::DPR3OpsIdx]
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? &ARM::ValueMappings[ARM::DPR3OpsIdx]
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: &ARM::ValueMappings[ARM::SPR3OpsIdx];
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: &ARM::ValueMappings[ARM::SPR3OpsIdx];
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break;
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break;
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case G_CONSTANT:
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case G_FRAME_INDEX:
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case G_FRAME_INDEX:
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OperandsMapping =
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OperandsMapping =
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getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
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getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
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@ -10,6 +10,8 @@
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define void @test_gep() { ret void }
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define void @test_gep() { ret void }
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define void @test_constants() { ret void }
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define void @test_fadd_s32() #0 { ret void }
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define void @test_fadd_s32() #0 { ret void }
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define void @test_fadd_s64() #0 { ret void }
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define void @test_fadd_s64() #0 { ret void }
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@ -225,6 +227,22 @@ body: |
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BX_RET 14, _, implicit %r0
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BX_RET 14, _, implicit %r0
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...
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...
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---
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---
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name: test_constants
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# CHECK-LABEL: name: test_constants
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: gprb }
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registers:
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- { id: 0, class: _ }
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body: |
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bb.0:
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%0(s32) = G_CONSTANT 42
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%r0 = COPY %0(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_fadd_s32
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name: test_fadd_s32
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# CHECK-LABEL: name: test_fadd_s32
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# CHECK-LABEL: name: test_fadd_s32
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legalized: true
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legalized: true
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